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LT3510IFE-PBF Datasheet(PDF) 9 Page - Linear Technology |
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LT3510IFE-PBF Datasheet(HTML) 9 Page - Linear Technology |
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9 / 28 page  LT3510 9 3510fc BLOCK DIAGRAM Figure 1. Block Diagram (One of Two Switching Regulators Shown) The LT3510 is dual channel, constant frequency, current mode buck converter with internal 2A switches. Each channel is identical with a common shutdown pin, internal regulator, oscillator, undervoltage detect, thermal shutdown and power-on reset. If the SHDN pin is taken below its 1.28V threshold the LT3510 will be placed in a low quiescent current mode. In this mode the LT3510 typically draws 9μA from VIN1 and <1μA from VIN2. In shutdown mode the PG is active with a typical sink capability of 50μA for VIN1 voltage greater than 2V. When the SHDN pin is opened or driven above 1.28V, the internal bias circuits turn on generating an internal regulated voltage, 0.8VFB, 0.975V RT/SYNC references, and a POR signal which sets the soft-start latch. As the RT/SYNC pin reaches its 0.975V regulation point, the internal oscillator will start generating two clock sig- nals 180° out of phase for each regulator at a frequency determined by the resistor from the RT/SYNCpintoground. Alternatively, if a synchronization signal is detected by the LT3510 at the RT/SYNC pin, clock signals 180° out of phase + + – INTERNAL REGULATOR AND REFERENCE OSCILLATOR AND AGC POR UNDERVOLTAGE TSD 7μA SHUTDOWN COMPARATOR RT/SYNC R3 VIN1 SHDN 3μA 1.28V GND S 0.8V LOWEST VOLTAGE POWER GOOD COMPARATOR SOFT-START RESET COMPARATOR 0.72V VC C RQ 3.25A CLK1 ONE CHANNEL CLK2 R S Q PRE DRIVER CIRCUITRY DROPOUT ENHANCEMENT SLOPE COMPENSATION + – + – VIN VOUT BST L1 D D R1 R2 C3 C SW IND FB PGOOD 3510 BD + + + 80mV C SS VC CLAMP SS CLAMP APPLICATIONS INFORMATION |
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