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LT3437EDD Datasheet(PDF) 4 Page - Linear Technology |
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LT3437EDD Datasheet(HTML) 4 Page - Linear Technology |
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4 / 28 page  4 LT3437 3437fc Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LT3437EDD/LT3437EFE are guaranteed to meet performance specifications from 0 °C to 125°C junction temperature. Specifications over the –40 °C to 125°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LT3437IDD/LT3437IFE are guaranteed and tested over the full –40 °C to 125 °C operating junction temperature range. The LT3437HFE is also tested to the LT3437 Electrical Characteristics table at 140 °C operating junction temperature. High junction temperatures degrade operating lifetimes. Note 3: Minimum input voltage is defined as the voltage where switching starts. Actual minimum input voltage to maintain a regulated output will depend upon output voltage and load current. See Applications Information. Note 4: Supply input current is the quiescent current drawn by the input pin. Its typical value depends on the voltage on the BIAS pin and operating state of the LT3437. With the BIAS pin at 0V, all of the quiescent current required to operate the LT3437 will be provided by the VIN pin. With the BIAS voltage above its minimum input voltage, a portion of the total quiescent current will be supplied by the BIAS pin. Supply sleep current is defined as the quiescent current during the “sleep” portion of Burst Mode operation. See Applications Information for determining application supply currents. Note 5: Minimum BIAS voltage is the voltage on the BIAS pin when IBIAS is sourced into the pin. Note 6: This is the minimum voltage across the boost capacitor needed to guarantee full saturation of the internal power switch. Note 7: Boost current is the current flowing into the BOOST pin with the pin held 3.3V above input voltage. It flows only during switch on time. Note 8: Gain is measured with a VC swing from 1.15V to 750mV. Note 9: Switch saturation voltage guaranteed by correlation to wafer level measurements for DD package parts. Note 10: The CSS threshold is defined as the value of current sourced into the CSS pin which results in an increase in sink current from the VC pin. See the Soft-Start section in Applications Information. IVIN Supply Quiescent Current BIAS = 0V, FB = 1.15V, VC = 0.8V, SYNC = 2V 1.35 2 mA BIAS = 5V, FB = 1.15V, VC = 0.8V, SYNC = 2V 0.475 1 mA Minimum BIAS Voltage (Note 5) 2.7 3.15 V IBIASS BIAS Sleep Current (Note 4) ● 110 180 µA IBIAS BIAS Quiescent Current SYNC = 2V 0.75 1 mA Minimum Boost Voltage (Note 6) ISW = 500mA 1.8 2.5 V Input Boost Current (Note 7) ISW = 0.5A 11 16 mA ISW = 0.25A 8 13 mA VREF Reference Voltage (VREF) 3.3V < VVIN < 60V ● 1.212 1.25 1.288 V VVIN = 80V ● 1.190 1.25 1.288 V IFB FB Input Bias Current 50 200 nA EA Voltage Gain (Note 8) 900 V/V EA Voltage gm dI(VC)= ±10µA 650 µMho EA Source Current FB = 1.15V 15 35 55 µA EA Sink Current FB = 1.35V 15 30 55 µA VC to SW gm 1A/V VC Switching Threshold VSYNC = 2V 500 mV VC High Clamp 1.5 1.75 2.1 V IPK SW Current Limit ● 400 650 900 mA SW VCESAT Switch Saturation Voltage ISW = 250mA ● 200 400 mV (Note 9) ISW = 500mA ● 400 800 mV Switching Frequency ● 140 200 240 kHz Maximum Duty Cycle 95 % Minimum SYNC Amplitude 1.5 2 V SYNC Frequency Range 240 500 kHz SYNC Input Impedance 50 k Ω ICSS CSS Current Threshold (Note 10) FB = 0V 4 10 16 µA The ● denotes the specifications which apply over the –40 °C to 140°C temperature range, otherwise specifications are at TJ = 25°C. VIN = 12V, SHDN = 12V, BIAS = 5V, FB = 1.25V, CSS/SYNC = 0V unless otherwise noted. ELECTRICAL CHARACTERISTICS |
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