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U4280 Datasheet(PDF) 5 Page - TEMIC Semiconductors |
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U4280 Datasheet(HTML) 5 Page - TEMIC Semiconductors |
5 / 9 page U4280BM Preliminary Information TELEFUNKEN Semiconductors Rev. A1, 10-Apr-97 5 (9) Electrical Characteristics VDD = 5 V, Tamb = 25°C, otherwise specified Parameters Test Conditions / Pins Symbol Min. Typ. Max. Unit Supply voltage range Pin 1 VDD 4.5 5.0 5.5 V Quiescent supply voltage Pin 1 IDD 6.0 11.6 mA FM input sensitivity RG = 50 W Pin 10 fi = 30 to 60 MHz fi = 70 to 120 MHz fi = 120 to 130 MHz VI Vi Vi 50 25 50 mV mV mV AM input sensitivity RG = 50 W Pin 12 fi = 0.4 to 35 MHz Vi 25 mV Oscillator input sensitivity RG = 50 W Pin 18 fi = 0.1 to 15 MHz Vi 100 mV Adjustable divider 1) 2 65535 Switching output, PRT Pin 5 IH = 1 mA IL = 1 mA IL = 0.1 mA VOH VOL VOL VDD – 0.4 0.4 0.1 V V V SWO1 to SWO3, AM/FM (open drain outputs) Pins 6 to 9 IL = 1 mA IL = 0.1 mA VOL VOL 0.4 0.1 V V LD (open drain) Pin 17 IL = 1 mA VOL 0.4 V Phase detector PDFM Pin 14 Output current 1 Output current 2 IO1 IO2 ±400 ±100 ±500 ±125 ±600 ±150 mA mA PDAM Pin 15 Output current 1 Output current 2 IO1 IO2 ±75 ±20 ±100 ±25 ±100 ±30 mA mA Analog output Pins 14 and 15 to VDD Pins 14 and 15 to GND I13,16 I13,16 0.1 –1 0.5 –2 mA mA I2bus inputs SCL, SDA H input voltage, Pins 2 and 3 L input voltage, Pins 2 and 3 VIH VIL 3 0 VDD 1.5 V V Output voltage ISDAH = 3 mA VO 0.4 V Clock frequency Pin 2 fSCL 0 110 kHz Bus timing Rise time SCL, SDA tr 1 ms Fall time SCL, SDA tf 300 ns “H” phase SCL tH 4 ms “L” phase SCL tL 4.7 ms Waiting time START twSTA 4 ms Set up time START thSTA 4 ms Set up time STOP tsSTA 4.7 ms Set up time DATA tsDAT 250 ns Hold time DATA thDAT 0 ms 1) FM input frequency is additionally divided by two (Pin 10). |
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