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LT3011EMSETR Datasheet(PDF) 10 Page - Linear Technology |
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LT3011EMSETR Datasheet(HTML) 10 Page - Linear Technology |
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10 / 16 page  LT3011 10 3011f APPLICATIONS INFORMATION in a small package, but they tend to have strong voltage and temperature coefficients, as shown in Figures 2 and 3. When used with a 5V regulator, a 16V 10μF Y5V capacitor can exhibit an effective value as low as 1μF to 2μF for the DC bias voltage applied and over the operating tempera- ture range. The X5R and X7R dielectrics result in more stable characteristics and are more suitable for use as the output capacitor. The X7R type has better stability across temperature, while the X5R is less expensive and is avail- able in higher values. Care still must be exercised when using X5R and X7R capacitors; the X5R and X7R codes only specify operating temperature range and maximum capacitance change over temperature. Capacitance change due to DC bias with X5R and X7R capacitors is better than Y5V and Z5U capacitors, but can still be significant enough to drop capacitor values below appropriate levels. Capaci- tor DC bias characteristics tend to improve as component case size increases, but expected capacitance at operating voltage should be verified. Voltage and temperature coefficients are not the only sources of problems. Some ceramic capacitors have a piezoelectric response. A piezoelectric device generates voltage across its terminals due to mechanical stress, simi- lar to the way piezoelectric accelerometer or microphone works. For a ceramic capacitor, the stress can be induced by vibrations in the system or thermal transients. PWRGD Flag and Timing Capacitor Delay The PWRGD flag is used to indicate that the ADJ pin volt- age is within 10% of the regulated voltage. The PWRGD pin is an open-collector output, capable of sinking 50μA of current when the ADJ pin voltage is low. There is no internal pull-up on the PWRGD pin; an external pull-up resistor must be used. When the ADJ pin rises to within 10% of its final reference value, a delay timer is started. At the end of this delay, programmed by the value of the capacitor on the CT pin, the PWRGD pin switches to a high impedance and is pulled up to a logic level by an external pull-up resistor. To calculate the capacitor value on the CT pin, use the following formula: C It VV TIME CT DELAY CT HIGH CT LOW = − • () ( ) Figure 4 shows a block diagram of the PWRGD circuit. At start-up, the timing capacitor is discharged and the PWRGD pin will be held low. As the output voltage increases and the ADJ pin crosses the 90% threshold, the JK flipflop is reset, and the 3μA current source begins to charge the timing capacitor. Once the voltage on the CT pin reaches the VCT(HIGH) threshold (approximately 1.7V at 25°C), the capacitor voltage is clamped and the PWRGD pin is set to a high impedance state. DC BIAS VOLTAGE (V) 3011 F02 20 0 –20 –40 –60 –80 –100 0 4 8 10 26 12 14 X5R Y5V 16 BOTH CAPACITORS ARE 16V, 1210 CASE SIZE, 10 F TEMPERATURE ( C) –50 40 20 0 –20 –40 –60 –80 –100 25 75 3011 F03 –25 0 50 100 125 Y5V X5R BOTH CAPACITORS ARE 16V, 1210 CASE SIZE, 10 F Figure 2. Ceramic Capacitor DC Bias Characteristics Figure 3. Ceramic Capacitor Temperature Characteristics |
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