4-87

TELCOM SEMICONDUCTOR, INC.

7

6

5

4

3

1

2

8

Paralleling Devices

Any number of TC7662B voltage converters may be

paralleled to reduce output resistance (Figure 5). The reser-

resistance would be approximately:

n (number of devices)

Changing the TC7662B Oscillator Frequency

It may be desirable in some applications (due to noise or

other considerations) to increase the oscillator frequency.

This is achieved by one of several methods described

below:

By connecting the BOOST Pin (Pin 1) to V

tor charge and discharge current is increased and, hence

the oscillator frequency is increased by approximately 3-1/

2 times. The result is a decrease in the output impedance

and ripple. This is of major importance for surface mount

applications where capacitor size and cost are critical.

Smaller capacitors, e.g., 0.1

µF, can be used in conjunction

with the Boost Pin in order to achieve similar output currents

10

µF. (Refer to graph of Output Source Resistance as a

Function of Oscillator Frequency).

Increasing the oscillator frequency can also be achieved

by overdriving the oscillator from an external clock as shown

in Figure 7. In order to prevent device latchup, a 1k

Ω resistor

must be used in series with the clock output. In a situation

where the designer has generated the external clock fre-

quency using TTL logic, the addition of a 10k

Ω pull-up-

resistor to V

quency with external clocking, as with internal clocking, will

be 1/2 of the clock frequency. Output transitions occur on the

positive-going edge of the clock.

Figure 6. Cascading Devices for Increased Output Voltage

1

2

3

4

8

7

6

5

V+

1

2

3

4

8

7

6

5

10

µF

10

µF

"n"

"1"

10

µF

VOUT

*VOUT = –nV+

+

+

+

TC7662B

TC7662B

10

µF

Cascading Devices

The TC7662B may be cascaded as shown to produce

larger negative multiplication of the initial supply voltage.

However, due to the finite efficiency of each device, the

practical limit is 10 devices for light loads. The output voltage

is defined by:

where n is an integer representing the number of devices

cascaded. The resulting output resistance would be ap-

proximately the weighted sum of the individual TC7662B

Figure 5. Paralleling Devices

1

2

3

4

8

7

6

5

TC7662B

+

V +

+

CMOS

GATE

10

µF

VOUT

10

µF

1 k

Ω

V +

Figure 7. External Clocking

It is also possible to increase the conversion efficiency

of the TC7662B at low load levels by lowering the oscillator

frequency. This reduces the switching losses, and is shown

in Figure 8. However, lowering the oscillator frequency will

cause an undesirable increase in the impedance of the

the frequency has been reduced. For example, the addition

of a 100pF capacitor between pin 7 (Osc) and V

the oscillator frequency to 1kHz from its nominal frequency

of 10kHz (multiple of 10), and thereby necessitate a corre-

100

µF).

1

2

3

4

8

7

6

5

TC7662B

V

+

1

2

3

4

8

7

6

5

TC7662B

C1

RL

C2

C1

"n"

"1"

+

TC7662B

CHARGE PUMP DC-TO-DC

VOLTAGE CONVERTER