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LT1964ES5-SD Datasheet(PDF) 10 Page - Linear Technology |
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LT1964ES5-SD Datasheet(HTML) 10 Page - Linear Technology |
10 / 16 page LT1964 10 1964fb PIN FUNCTIONS ADJ (Adjustable Devices only): For the Adjustable LT1964, this is the Input to the Error Amplifier. The ADJ pin has a bias current of 30nA that flows out of the pin. The ADJ pin voltage is –1.22V referenced to ground, and the output voltage range is –1.22V to –20V. A parasitic diode exists between the ADJ pin and the input of the LT1964. The ADJ pin cannot be pulled more negative than the input during normal operation, or more than 0.5V more negative than the input during a fault condition. BYP: The BYP Pin is used to Bypass the Reference of the LT1964 to Achieve Low Noise Performance from the Regulator. A small capacitor from the output to this pin will bypass the reference to lower the output voltage noise. A maximum value of 0.01μF can be used for reducing output voltage noise to a typical 30μVRMS over a 10Hz to 100kHz bandwidth. If not used, this pin must be left unconnected. Exposed Pad (DFN Package Only): IN. Connect to IN (Pins 7, 8) at the PCB. GND: Ground. IN: Power is Supplied to the Device Through the Input Pin. A bypass capacitor is required on this pin if the device is more than six inches away from the main input filter capacitor. In general, the output impedance of a battery rises with frequency, so it is advisable to include a bypass capacitor in battery-powered circuits. A bypass capacitor in the range of 1μF to 10μF is sufficient. OUT: The Output Supplies Power to the Load. A minimum output capacitor of 1μF is required to prevent oscillations. Larger output capacitors will be required for applications with large transient loads to limit peak voltage transients. A parasitic diode exists between the output and the input. The output cannot be pulled more negative than the input during normal operation, or more than 0.5V below the input during a fault condition. See the Applications Information section for more information on output capacitance and reverse output characteristics. SHDN: The SHDN Pin is used to put the LT1964 into a Low Power Shutdown State. The SHDN pin is referenced to the GND pin for regulator control, allowing the LT1964 to be driven by either positive or negative logic. The output of the LT1964 will be off when the SHDN pin is pulled within ±0.8V of GND. Pulling the SHDN pin more than –1.9V or +1.6V will turn the LT1964 on. The SHDN pin can be driven by 5V logic or open collector logic with a pull-up resistor. The pull-up resistor is required to supply the pull-up current of the open collector gate, normally several microamperes, and the SHDN pin current, typi- cally 3μA out of the pin (for negative logic) or 6μA into the pin (for positive logic). If unused, the SHDN pin must be connected to VIN. The device will be shut down if the SHDN pin is open circuit. For the LT1964-BYP, the SHDN pin is internally connected to VIN. A parasitic diode exists between the SHDN pin and the input of the LT1964. The SHDN pin cannot be pulled more negative than the input during normal operation, or more than 0.5V below the input during a fault condition. |
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