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TC14433AEJG Datasheet(PDF) 5 Page - TelCom Semiconductor, Inc |
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TC14433AEJG Datasheet(HTML) 5 Page - TelCom Semiconductor, Inc |
5 / 10 page 3-131 TELCOM SEMICONDUCTOR, INC. 7 6 5 4 3 1 2 8 3-1/2 DIGIT A/D CONVERTERS TC14433 TC14433A PIN DESCRIPTIONS (Cont.) Pin No. Pin No. Pin No. 24-Pin 24-Pin 28-Pin PDIP/CerDip SOIC PLCC Symbol Description 16 16 19 DS4 Digit select pins — The digit select output goes high when the respective digit is selected. The MSD (1/2 digit) turns on immediately after an EOC pulse. 17 17 20 DS3 The remaining digits turn on in sequence from MSD to LSD. 18 18 21 DS2 To ensure that the BCD data has settled, an inter-digit blanking time of two clock periods is included. 19 19 23 DS1 Clock frequency divided by 80 equals multiplex rate. For example, a system clock of 60 kHz gives a multiplex rate of 0.8 kHz. 20 20 24 Q0 See Figure 12 for digit select timing diagram. 21 21 25 Q1 BCD data output pins — Multiplexed BCD outputs contain three full digits of information during digit select DS2, DS3, DS4. 22 22 26 Q2 During DS1, the 1/2 digit, overrange, underrange and polarity information is available. 23 23 28 Q3 Refer to truth table. 24 24 28 VDD Positive power supply — This is the most positive power supply pin. 8,15, 22 NC Not Used. CIRCUIT DESCRIPTION The TC14433 CMOS IC becomes a modified dual- slope A/D with a minimum of external components. This IC has the customary CMOS digital logic circuitry, as well as CMOS analog circuitry. It provides the user with digital functions (such as counters, latches, multiplexers) and analog functions (such as operational amplifiers and com- parators) on a single chip. Features of this system include auto-zero, high input impedances and auto-polarity. Low power consumption and a wide range of power supply voltages are also advan- tages of this CMOS device. The system's auto-zero function compensates for the offset voltage of the internal amplifiers and comparators. In this "ratiometric system," the output reading is the ratio of the unknown voltage to the reference voltage, where a ratio of 1 is equal to the maximum count of 1999. It takes approximately 16,000 clock periods to com- plete one conversion cycle. Each conversion cycle may be divided into 6 segments. Figure 7 shows the conversion cycle in 6 segments for both positive and negative inputs. Segment 1 — The offset capacitor (CO), which com- pensates for the input offset voltages of the buffer and integrator amplifiers, is charged during this period. How- ever, the integrator capacitor is shorted. This segment requires 4000 clock periods. Segment 2 — During this segment, the integrator output decreases to the comparator threshold voltage. At this time, a number of counts equivalent to the input offset Figure 7. Integrator Waveforms at Pin 6 Figure 8. Equivalent Circuit Diagrams of the Analog Section During Segment 4 of the Timing Cycle START 1 2 3 45 6 TYPICAL POSITIVE INPUT VOLTAGE TYPICAL NEGATIVE INPUT VOLTAGE TIME SEGMENT NUMBER END VX VX C1 COMPARATOR R1 VX BUFFER INTEGRATOR + – + – + – voltage of the comparator is stored in the offset latches for later use in the auto-zero process. The time for this segment is variable and less than 800 clock periods. |
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