IN

16C554PL/IN16C554TQ

QUAD-UART

ASYNCHRONOUS COMMUNICATIONS ELEMENT

NOVEMBER 2002-REVISED AUG 2006

Decimal divisor to generate 16 x Clock

Desired baud rate

1.8432MHz

3.6864MHz

7.3728MHz

14.7456MHz

50

2304

4608

9216

18432

75

1536

3072

6144

12288

134.5

857

1714

3428

6856

150

768

1536

3072

6144

300

384

768

1536

3072

600

192

384

768

1536

1200

96

192

384

768

1800

64

128

256

512

2000

58

116

232

464

2400

48

96

192

384

3600

32

64

128

256

4800

24

48

96

192

7200

16

32

64

128

9600

12

24

48

96

19.2K

6

12

24

48

38.4K

3

6

12

24

57.6K

2

4

8

16

115.2K

1

2

4

8

230.4K

-

1

2

4

460.8K

-

-

1

2

921.6K

-

-

-

1

5.3. Line Status Register

This register provides status information to the CPU concerning the data transfer.

Bit 0 : Data Ready(DR) indicator. Bit 0 is set to a logic 1 whenever a complete incoming character has

been received and transferred into the Receiver Buffer Register or the FIFO. This bit is cleared by

reading all of the data in the Receiver Buffer Register of the FIFO.

Bit 1 : Overrun Error(OE) indicator. Bit 1 indicates that data in the Receiver Buffer Register was not

read by the CPU before the next character was transferred into the Receiver Buffer Register, thereby

destroying the previous character. This bit is set to a logic 1 when overrun occurs and cleared

whenever the CPU reads the contents of the Line Status Register. If the FIFO mode data continues to

fill the FIFO beyond the trigger level, an overrun error will occur only after the FIFO is full and the next

character has been completely received in the shift register. OE is indicated to the CPU as soon as it

happens. The character in the shift register is overwritten, but it is not transferred to the FIFO.

Bit 2 : Parity Error indicator. Bit 2 is set to a logic 1 upon detection of a parity error and is reset to a

logic 0 whenever CPU reads the contents of the Line Status Register. In the FIFO mode, this error is

revealed to CPU when its associated character is at the top of the FIFO.

Bit 3 : Framing Error indicator. Bit 3 indicates that the received character did not have a valid stop bit.

This bit is set to a logic 1 whenever the stop bit following the last data bit or parity bit is detected as a

logic 0 bit. It is reset to a logic 0 whenever CPU reads the contents of the Line Status Register. In the

FIFO mode, this error is revealed to CPU when its associated character is at the top of the FIFO.

When this error has been detected, CPU assumes it due to a next start bit, so it samples this start bit

twice and the take the data.

Rev. 01