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IN74LV574DW Datasheet(PDF) 1 Page - IK Semicon Co., Ltd |
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IN74LV574DW Datasheet(HTML) 1 Page - IK Semicon Co., Ltd |
1 / 8 page TECHNICAL DATA IN74LV574 Octal D-type flip-flop; positive edge-trigger (3-State) N SUFFIX PLASTIC DIP DW SUFFIX SO 1 20 1 20 ORDERING INFORMATION IN74LV574N Plastic DIP IN74LV574DW SOIC TA = -40° to 125° C for all packages The 74LV574 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT574. The 74LV574 is an octal D-type flip–flop featuring separate D-type inputs for each flip-flop and non-inverting 3-state outputs for oriented applications. A clock (CP) and an output enable (OE) input are common to all flip-flops. The eight flip-flops will store the state of their individual D- inputs that meet the set-up and hold times requirements on the LOW-to- HIGH CP transition. When OE is LOW, the contents of the eight flip-flops are available at the outputs. When OE is HIGH, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops. • Output voltage levels are compatible with input levels of CMOS, NMOS and TTL ICS • Supply voltage range: 1.0 to 5.5 V • Low input current: 1.0 µА; 0.1 µА at Т = 25 °С • High Noise Immunity Characteristic of CMOS Devices FUNCTION TABLE Inputs Output Output Enable Clock D Q L H H L L L L L,H, X no change H X X Z H= high level L = low level X = don’t care Z = high impedance PIN ASSIGNMENT LOGIC DIAGRAM PIN 20=VCC PIN 10 = GND 1 |
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