Prepare by Telecom Group

3

Rev. D

3/29/2002

Supertex, Inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 744-0100 FAX: (408) 222-4895 www.supertex.com

HV9904

Pinout

1

2

3

4

5

6

7

8

HV9904

+Vin

Vdd

AGND

PS

GATE

NC

PGND

NS

Pin Description

the constant voltage VDD internal supply for the PWM. It can

accept DC input voltages in the range of 10 to 400 Volts.

supply pin for the PWM circuits. It must be bypassed with a

capacitor capable of storing sufficient energy so that the voltage

does not decay below the UVLO threshold during the time when

the input voltage is below the minimum required by the regulator.

NC – No internal connection to this pin.

AGRD – Common connection for analog circuits.

GATE – This is the PWM output for driving the gate of an N-

channel external MOSFET.

PGRD – Common connection for GATE drive circuit.

NS – This is negative sense input to the PWM control circuit.

PS – This is positive sense input to the PWM control circuit

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Functional Block Diagram

Regulator

UVLO

Vdd

+Vin

Vdd

AGND

Integrator

Reference

Vref

Variable Frequency and

Duty Cycle Oscillator

Gate

Driver

Differential

Sense

GATE

PGND

PS

NS

Functional Description

On initial power application the high input voltage (10V to 400V)

linear regulator charges the capacitor connected to Vdd and seeks

to provide a stable supply for the internal circuitry and gate drive to

the external MOSFET. Under voltage lockout (UVLO) holds the

oscillator disabled and reset to its lowest frequency state until the

Vdd supply rises above 8Volts assuring sufficient gate drive

voltage for the external MOSFET. Once Vdd is above the UVLO

threshold the oscillator is enabled and the external MOSFET is

driven via the gate driver at the oscillator frequency. The UVLO

has a 0.5V hysteresis to prevent false triggering due to ripple on

Vdd.

The duty cycle of the oscillator output and thus the on time of the

MOSFET is determined by a feed forward circuit that sets the

maximum on time based on the instantaneous value of the input

voltage, thus avoiding core saturation of the magnetic elements.

The oscillator is initially operating at its lowest frequency and

continues to operate at this low frequency for several cycles to

assure that a stable equilibrium state is reached. After this initial

delay the feedback circuit is enabled and the oscillator frequency is

increased in small steps on oscillator cycles until the PWM output

(current or voltage) reaches the programmed value. Since the rate

of increase in frequency is a function of the frequency the oscillator

frequency will rise exponentially.

The differential sense circuit monitors the programming node

(voltage on current sense resistor for constant average current

control or voltage on resistive divider for constant average voltage

control) using an integrator lock loop feedback to obtain a stable

average value from even a discontinuous signal. As long as this

average value is less than 2.5V the oscillator frequency is

incremented. When the average value reaches 2.5V the oscillator

frequency incrementing is halted. If the average value exceeds

2.5V then the oscillator frequency is decremented. In this manner

the oscillator frequency is dithered to maintain output regulation

while the feed forward sensing of the input voltage maintains a

fixed value of energy transfer per oscillator cycle.

Line regulation is controlled by the instantaneous feed forward

sensing of the input voltage, thus the PWM can easily track a full

wave rectified sine wave of input voltage at 50Hz, 60Hz or 400Hz

provided that the capacitor connected at Vdd can store sufficient

energy to prevent decay below the UVLO threshold during the time

when the resulting input voltage at +Vin is below 10V. For a 50Hz

rectified sine wave a 1

µF capacitor connected to Vdd is sufficient

to guarantee stable operation at 50Hz.

Load regulation is controlled via the feedback sensing circuit by

adjusting the oscillator frequency to maintain average energy

transfer consistent with the load conditions. For relatively stable

load conditions this method achieves excellent regulation. For a

constant load the switching frequency will be nearly constant with a

dither of a few kHz helping to meet FCC conducted emissions

requirements.