TECHNICAL DATA

IN74AC74

Dual D Flip-Flop with Set and Reset

High-Speed Silicon-Gate CMOS

ORDERING INFORMATION

IN74AC74N Plastic

IN74AC74D SOIC

The IN74AC74 is identical in pinout to the LS/ALS74, HC/HCT74.

The device inputs are compatible with standard CMOS outputs; with

pullup resistors, they are compatible with LS/ALS outputs.

This device consists of two D flip-flops with individual Set, Reset,

and Clock inputs. Information at a D-input is transferred to the

corresponding Q output on the next positive going edge of the clock input.

Both Q and Q outputs are available from each flip-flop. The Set and Reset

inputs are asynchronous.

• Outputs Directly Interface to CMOS, NMOS, and TTL

• Operating Voltage Range: 2.0 to 6.0 V

• Low Input Current: 1.0 μA; 0.1 μA @ 25°C

• High Noise Immunity Characteristic of CMOS Devices

• Outputs Source/Sink 24 mA

Rev. 00

PIN ASSIGNMENT

LOGIC DIAGRAM

PIN 7 = GND

FUNCTION TABLE

Inputs

Outputs

Set

Reset

Clock

Data

Q

Q

L

H

X

X

H

L

H

L

X

X

L

H

L

L

X

H

*

H

*

X

H

H

H

H

L

H

H

L

L

H

H

H

L

X

No Change

H

H

H

X

No Change

H

H

X

No Change

*Both outputs will remain high as long as Set

and Reset are low, but the output states are

unpredictable if Set and Reset go high

simultaneously.

X = don’t care