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RBHV57708DG Datasheet(PDF) 2 Page - Supertex, Inc |
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RBHV57708DG Datasheet(HTML) 2 Page - Supertex, Inc |
2 / 5 page 2 Symbol Parameter Min Max Units V DD Logic supply voltage 4.5 5.5 V VPP Output voltage 8 80 V V IH High-level input voltage V DD -0.5V V V IL Low-level input voltage 0 0.5 V fCLK Clock frequency per register 8 MHz T A Operating free-air temperature Plastic -40 +85 °C Ceramic -55 +125 Note: Power-up sequence should be the following: 1. Connect ground. 2. Apply VDD. 3. Set all inputs (Data, CLK, Enable, etc.) to a known state. 4. Apply VPP. 5. The VPP should not drop below VDD or float during operation. Power-down sequence should be the reverse of the above. Electrical Characteristics (over recommended operating conditions unless noted, T A=-40°C to +85°C) DC Characteristics Symbol Parameter Min Max Units Conditions IDD VDD supply current 15 mA VDD = VDD max fCLK = 8MHz I PP High voltage supply current 100 µA Outputs high 100 µA Outputs low IDDQ Quiescent VDD supply current 100 µA All VIN = VDD V OH High-level output HV OUT 65 V I O= -15mA, VPP = 80V Data out VDD - 0.5 V IO= -100µA VOL Low-level output HVOUT 7V IO = 12mA, VPP = 80V Data out 0.5 V I O= 100µA IIH High-level logic input current 1 µAVIH = VDD IIL Low-level logic input current -1 µAVIL = 0V V OC High voltage clamp diode 1 V I OC = 1mA Recommended Operating Conditions AC Characteristics (T A = 85°C max. Logic signal inputs and Data inputs have tr, tf ≤ 5ns [10% and 90% points]) Symbol Parameter Min Max Units Conditions f CLK Clock frequency 8 MHz Per Register tWL,tWH Clock width high or low 62 ns tSU Data set-up time before clock rises 10 ns t H Data hold time after clock rises 15 ns tON, tOFF Time from latch enable to HVOUT 500 ns CL = 15pF t DHL Delay time clock to data high to low 70 ns C L = 15pF t DLH Delay time clock to data low to high 70 ns C L = 15pF tDLE* Delay time clock to LE low to high 25 ns t WLE Width of LE pulse 25 ns t SLE LE set-up time before clock rises 0 ns * t DLE is not required but is recommended to produce stable HV outputs and thus minimize power dissipation and current spikes (allows internal SR output to stabilize). HV57708 |
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