11

LT1641-1/LT1641-2

164112fc

APPLICATIO S I FOR ATIO

TIMER

SENSE

GATE

87

6

54

2

1

3

D1

CMPZ

5248B

GND

PWRGD

FB

R5

10

Ω

5%

ON

R1

294k

1%

48V

UV = 37V

GND

1641-1 F12

R2

10.2k

1%

C2

0.68

µF

R6,

1k, 5%

0.01

Ω

C1

10nF

R3

143k

1%

R4

4.22k

1%

R7

47k

5%

+

220

µF

Q2

MMBT5551LT1

LT1641-1

ACTIVE LOW

ENABLE MODULE

ON/OFF

Q1

IRF530

SHORT

PIN

Figure 12. Active Low Enable Module

R1

SENSE

R2

LT1641-1

Figure 13. Gate Drive vs Supply Voltage

8

18

16

14

12

10

8

6

4

2

0

1641-1

F13

13

18

23

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

Layout Considerations

To achieve accurate current sensing, a Kelvin connection

is recommended. The minimum trace width for 1oz cop-

per foil is 0.02" per amp to make sure the trace stays at a

reasonable temperature. 0.03" per amp or wider is recom-

mended. Note that 1oz copper exhibits a sheet resistance

of about 530

µΩ/ . Small resistances add up quickly in

high current applications. To improve noise immunity, put

the resistor divider to the ON pin close to the chip and keep

ON pin to GND also helps reject induced noise. Figure 14

shows a layout that addresses these issues.