7

LT1641-1/LT1641-2

164112fc

ON

GATE

5V

1.313V

1V

1.233V

FB

PWRGD

1V

1.313V

1V

1.233V

GATE

47mV

TI I G DIAGRA S

Figure 2. ON to GATE Timing

Figure 3. FB to PWRGD Timing

Figure 4. SENSE to GATE Timing

APPLICATIO S I FOR ATIO

Hot Circuit Insertion

When circuit boards are inserted into a live backplane, the

supply bypass capacitors on the boards draw high peak

currents from the backplane power bus as they charge up.

The transient currents can permanently damage the con-

nector pins and glitch the system supply, causing other

boards in the system to reset.

The chip is designed to turn on a board’s supply voltage in

a controlled manner, allowing the board to be safely

inserted or removed from a live backplane. The chip also

provides undervoltage and overcurrent protection while a

power good output signal indicates when the output

supply voltage is ready.

Power-Up Sequence

The power supply on a board is controlled by placing an

external N-channel pass transistor (Q1) in the power path

capacitor C1 provides control of the GATE slew rate.

Resistor R6 provides current control loop compensation

while R5 prevents high frequency oscillations in Q1.

Resistors R1 and R2 provide undervoltage sensing.

After the power pins first make contact, transistor Q1 is

turned off. If the voltage at the ON pin exceeds the turn-on

undervoltage lockout threshold, and the voltage on the

TIMER pin is less than 1.233V, transistor Q1 will be turned

on (Figure 6). The voltage at the GATE pin rises with a slope

equal to 10

µA/C1 and the supply inrush current is set at

be limited by the internal current limit circuitry which

adjusts the voltage on the GATE pin to maintain a constant

voltage across the sense resistor.

Once the voltage at the output has reached its final value,

as sensed by resistors R3 and R4, the PWRGD pin goes

high.