F75363

F75363

July, 2007

V0.27P

-4-

0

Start By

Master

0

1

011

00

D7

D6

D5

D4

D3

D2

D1

D0

Ack

by

363

R/W

Ack

by

363

SCL

SDA

D7

D6

D5

D4

D3

D2

D1

D0

Stop

by

Master

SCL

SDA (Continued)

78

0

7

8

0

78

Frame 2

Internal Index Register Byte

(Continued)

Frame 3

Data Byte

Frame 1

Serial Bus Address Byte

Figure 1. Serial Bus Write to Internal Address Register followed by the Data Byte

0

Start By

Master

0

1

011

00

D7

D6

D5

D4

D3

D2

D1

D0

Ack

by

363

R/W

Ack

by

363

SCL

SDA

78

0

7

8

0

Frame 2

Internal Index Register Byte

Frame 1

Serial Bus Address Byte

Figure 2. Serial Bus Write to Internal Address Register Only

Stop by

Master

(c) Serial bus read from a register with the internal address register prefer to desired location

0

Start By

Master

0

1

011

00

D7

D6

D5

D4

D3

D2

D1

D0

Ack

by

Master

R/W

Ack

by

363

SCL

SDA

78

0

7

8

0

Frame 2

Internal Index Register Byte

Frame 1

Serial Bus Address Byte

Figure 3. Serial Bus Read from Internal Address Register

Stop by

Master

(d) Alert Response Address

0

Start By

Master

0

0011

00

01

001100

Ack

by

Master

R/W

Ack

by

363

SCL

SDA

78

0

7

8

0

Frame 2

Device Address

Frame 1

Alert Response Address

Figure 4. Alert Response Address

Stop by

Master

6.3 Typical Operating Characteristics

(a) Temperature Error vs.D+/D- Capacitance