Dec., 2007

V0.22P

-3-

F71612

P

- Power.

Pin No

Pin Name

Type

PWR

Description

1

D+

VDD D+. Different data bus conforming to USB standard. Internal pull

high 1.5kΩ.

2

D-

VDD D-. Different data bus conforming to USB standard.

3

PSOUT#

VDD Panel Switch Output. This pin is low active and pulse output. It is

power on request output.

4

VDD This pin is for wake up function.

For Portable Product

Pull this pin to high for USB wake up.

For MB System Product

Pull this pin to high and suggest

connecting with one of S4/S5/PWROK/GPIO pin.

MB System in S4/S5 state: Wake up signal will be asserted by

PSOUT# pin in S4/S5 state.

MB System in S3 state: Wake up signal will be asserted by USB

interface in S3 state.

5

VDD 12MHz/48MHz clock input.

6

XTALOUT

VDD 12MHz/48MHz clock output.

7

PWCTL

VDD RX_LR learning power control pin. Suggest external pull high to

3.3V and the clock input source will be selected to 12MHz input.

8

GND

P

VDD Ground pin.

9

SCL

VDD I2C interface serial clock

10

SDA

VDD I2C interface serial data

11

TX1

VDD IR transmits port 1.

Pull down 100k resister to ground

TX/RX functions selection.

No resister connects to ground

RX function only.

12

TX0

VDD IR transmits port 0.

Pull down 100k resister to ground ( TX/RX functions

selection.

No resister connects to ground ( RX function only.

(P.S One of TX pins pull down 100K resister to ground, chip

feature will be selected to TX and RX functions, if not, chip

will be selected to RX function only.)

13

LED#

OD16_5V

VDD LED output pin.

14

RX_LR#

VDD IR receiver port1 ( wide band for learning)

15

RX_NR#

VDD IR receiver port0 (long range)