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XD010-51S-D4F Datasheet(PDF) 2 Page - SIRENZA MICRODEVICES |
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XD010-51S-D4F Datasheet(HTML) 2 Page - SIRENZA MICRODEVICES |
2 / 5 page XD010-51S-D4F 902-928 MHz 15W Power Amp Module 303 S. Technology Court Phone: (800) SMI-MMIC http://www.sirenza.com Broomfield, CO 80021 2 EDS-105061 Rev E Pin Description Pin # Function Description 1 RF Input Module RF input. This pin is internally connected to DC ground. Do not apply DC voltages to the RF leads. Care must be taken to protect against video transients that may damage the active devices. 2VD1 This is the drain voltage for the first stage. Nominally +28Vdc 3VD2 This is the drain voltage for the 2nd stage of the amplifier module. The 2nd stage gate bias is temperature compensated to maintain constant quiscent drain current over the operating temperature range. See Note 1. 4 RF Output Module RF output. This pin is internally connected to DC ground. Do not apply DC voltages to the RF leads. Care must be taken to protect against video transients that may damage the active devices. Flange Gnd Exposed area on the bottom side of the package needs to be mechanically attached to the ground plane of the board for optimum thermal and RF performance. See mounting instructions in application note AN-060 on Sirenza’s web site. Simplified Device Schematic Absolute Maximum Ratings Parameters Value Unit 1st Stage Bias Voltage (VD1 )35 V 2nd Stage Bias Voltage (VD2)35 V RF Input Power +20 dBm Load Impedance for Continuous Operation With- out Damage 5:1 VSWR Output Device Channel Temperature +200 ºC Operating Temperature Range -20 to +90 ºC Storage Temperature Range -40 to +100 ºC Operation of this device beyond any one of these limits may cause per- manent damage. For reliable continuous operation see typical setup val- ues specified in the table on page one. Caution: ESD Sensitive Appropriate precaution in handling, packaging and testing devices must be observed. Note 1: The internally generated gate voltage is thermally compen- sated to maintain constant quiescent current over the temper- ature range listed in the data sheet. No compensation is provided for gain changes with temperature. This can only be accomplished with AGC external to the module. Note 2: Internal RF decoupling is included on all bias leads. No addi- tional bypass elements are required, however some applica- tions may require energy storage on the drain leads to accommodate time-varying waveforms. Note 3: This module was designed to have its leads hand soldered to an adjacent PCB. The maximum soldering iron tip tempera- ture should not exceed 700° F, and the soldering iron tip should not be in direct contact with the lead for longer than 10 seconds. Refer to app note AN060 (www.sirenza.com) for fur- ther installation instructions. Temperature Compensation Bias Network V D2 D1 V RF 1 Q1 Q2 2 3 4 Case Flange = Ground in out RF Quality Specifications Parameter Unit Typical ESD Rating Human Body Model, JEDEC Document - JESD22-A114-B V 8000 MTTF 85oC Leadframe, 200oC Channel Hours 1.2 X 106 |
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