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SN75DP118 Datasheet(PDF) 2 Page - Texas Instruments |
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SN75DP118 Datasheet(HTML) 2 Page - Texas Instruments |
2 / 18 page DATA FLOW BLOCK DIAGRAM NC DPadj GND HPD_OUT ML_IN 0(p) VDD CAD_OUT GND ML_IN 0(n) VCC ML_OUT 0(p) CAD_INV VCC ML_OUT 0(n) CAD_IN SN75DP118 VCC HPD_IN LP PACKAGE CAD_OUT HPD_OUT 1 GND CAD_IN ML_IN 0(p) VDD HPD_IN GND ML_IN 0(n) VCC DPadj 2 3 4 5 6 7 8 11 10 12 13 14 15 16 17 35 36 34 33 32 SN75DP118 9 18 VCC NC 19 26 25 ML_OUT 0(p) CAD_INV VCC ML_OUT 0(n) 31 30 29 27 24 23 22 21 20 28 LP SN75DP118 SLLS916A – SEPTEMBER 2008 – REVISED SEPTEMBER 2008..................................................................................................................................... www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 2 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): SN75DP118 |
Similar Part No. - SN75DP118_1 |
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Similar Description - SN75DP118_1 |
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