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TMP320CC6713BGDPA20EP Datasheet(PDF) 2 Page - Texas Instruments |
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TMP320CC6713BGDPA20EP Datasheet(HTML) 2 Page - Texas Instruments |
2 / 123 page Contents SM320C6713-EP SM320C6713B-EP FLOATING-POINT DIGITAL SIGNAL PROCESSORS SGUS049H – AUGUST 2003 – REVISED SEPTEMBER 2008 www.ti.com 1 FEATURES .......................................................................................................................... 5 2 SUPPORTS DEFENSE, AEROSPACE, AND MEDICAL APPLICATIONS ........................................ 5 3 DEVICE INFORMATION ......................................................................................................... 6 3.1 Description .................................................................................................................... 9 3.2 Device Characteristics ..................................................................................................... 11 3.3 Functional Block and CPU (DSP Core) Diagram ...................................................................... 12 4 OVERVIEW ........................................................................................................................ 13 4.1 CPU (DSP Core) Description ............................................................................................. 13 4.2 Memory Map Summary .................................................................................................... 14 4.3 L2 Memory Structure Expanded .......................................................................................... 16 4.4 Peripheral Register Descriptions ......................................................................................... 17 4.5 Signal Groups Description ................................................................................................ 25 5 DEVICE CONFIGURATIONS ................................................................................................. 30 5.1 Device Configurations at Device Reset ................................................................................. 30 5.2 Peripheral Pin Selection at Device Reset ............................................................................... 31 5.3 Peripheral Selection/Device Configurations Via the DEVCFG Control Register ................................... 31 5.4 Multiplexed Pins ............................................................................................................ 32 5.5 Configuration Examples ................................................................................................... 36 5.6 Debugging Considerations ................................................................................................ 42 6 TERMINAL FUNCTIONS ....................................................................................................... 42 6.1 Development Support ...................................................................................................... 49 6.2 Device and Development-Support Tool Nomenclature ................................................................ 50 6.2.1 Device Development Evolutionary Flow ...................................................................... 50 6.2.2 Support Tool Development Evolutionary Flow ............................................................... 50 6.3 Ordering Nomenclature .................................................................................................... 51 6.4 Documentation Support ................................................................................................... 51 7 REGISTER INFORMATION ................................................................................................... 53 7.1 CPU Control Status Register (CSR) Description ....................................................................... 53 7.2 Cache Configuration (CCFG) Register Description (13B) ............................................................ 54 7.3 Interrupts and Interrupt Selector ......................................................................................... 55 7.4 External Interrupt Sources ................................................................................................ 57 7.5 EDMA Module and EDMA Selector ...................................................................................... 58 8 PLL and PLL Controller ....................................................................................................... 62 8.1 PLL Registers ............................................................................................................... 63 9 MULTICHANNEL AUDIO SERIAL PORT (McASP) PERIPHERALS ............................................. 69 9.1 McASP Block Diagram .................................................................................................... 69 9.2 Multichannel Time Division Multiplexed (TDM) Synchronous Transfer Mode ...................................... 71 9.3 Burst Transfer Mode ....................................................................................................... 71 9.4 Supported Bit Stream Formats for TDM and Burst Transfer Modes ................................................ 72 9.5 Digital Audio Interface Transmitter (DIT) Transfer Mode (Transmitter Only) ....................................... 72 9.6 McASP Flexible Clock Generators ....................................................................................... 73 9.7 McASP Error Handling and Management ............................................................................... 73 9.8 McASP Interrupts and EDMA Events .................................................................................... 74 9.9 I 2C ............................................................................................................................ 74 10 LOGIC AND POWER SUPPLY .............................................................................................. 76 10.1 General-Purpose Input/Output (GPIO) .................................................................................. 76 10.2 Power-Down Mode Logic .................................................................................................. 77 10.2.1 Triggering, Wake-Up, and Effects ............................................................................. 77 10.3 Power-Supply Sequencing ................................................................................................ 78 10.3.1 System-Level Design Considerations ......................................................................... 79 Contents 2 Submit Documentation Feedback |
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