D

FF

Q

D

Q

FF

D

Q

FF

D

Q

FF

Data From

Shift Register

Data From

Shift Register

Write Configuration

Pulse

Write Pulse

Read Pulse

Data From

Shift Register

Write Polarity Pulse

Polarity

Inversion

Register

Input

Port

Register

Output

Port

Register

Configuration

Register

GND

Input Port

Register Data

Polarity

Register Data

ESD Protection Diode

P7−P1

Output Port

Register Data

I

PCA9557

SIMPLIFIED SCHEMATIC DIAGRAM OF P7–P1

A.

On power up or reset, all registers return to default values.

connected to a positive supply through a pullup resistor when connected to the output stages of a device. Data

transfer may be initiated only when the bus is not busy.

the SDA input/output while the SCL input is high (see Figure 1). After the start condition, the device address byte

is sent, most-significant bit (MSB) first, including the data direction bit (R/W).

After receiving the valid address byte, this device responds with an acknowledge (ACK), a low on the SDA

input/output during the high of the ACK-related clock pulse. The address (A2–A0) inputs of the slave device must

not be changed between the start and the stop conditions.

stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as control

commands (start or stop) (see Figure 2).

A stop condition, a low-to-high transition on the SDA input/output while the SCL input is high, is sent by the

master (see Figure 1).

Any number of data bytes can be transferred from the transmitter to the receiver between the Start and the Stop

conditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before

the receiver can send an ACK bit. The device that acknowledges must pull down the SDA line during the ACK

clock pulse, so that the SDA line is stable low during the high pulse of the ACK-related clock period (see

Figure 3). When a slave receiver is addressed, it must generate an ACK after each byte is received. Similarly,

the master must generate an ACK after each byte that it receives from the slave transmitter. Setup and hold

times must be met to ensure proper operation.

Copyright © 2005–2008, Texas Instruments Incorporated

Submit Documentation Feedback

5

Product Folder Link(s): PCA9557