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PCA9557RGYR Datasheet(PDF) 10 Page - Texas Instruments |
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PCA9557RGYR Datasheet(HTML) 10 Page - Texas Instruments |
10 / 36 page Reads A2 0 0 S 1 1 A1 A0 0 A A Data from Register Slave Address Slave Address R/W ACK From Slave Command Byte S A2 0 0 1 1 A1 A0 R/W 1 A Data A Data Data from Register NA P Last Byte At this moment, master-transmitter becomes master-receiver, and slave-receiver becomes slave-transmitter ACK From Slave ACK From Slave ACK From Master NACK From Master First Byte SCL SDA Start Condition R/W Read From Port Data Into Port Stop Condition ACK From Master NACK From Master ACK From Slave Data From Port Slave Address Data From Port 1 9 8 7 6 5 4 3 2 A2 0 0 S 1 1 A1 A0 1 A Data 1 Data 4 A NA P Data 2 Data 3 Data 4 tph tps Data 5 PCA9557 SCPS133I – DECEMBER 2005 – REVISED JUNE 2008.................................................................................................................................................... www.ti.com The bus master first must send the PCA9557 address with the LSB set to a logic 0 (see Figure 4 for device address). The command byte is sent after the address and determines which register is accessed. After a restart, the device address is sent again but, this time, the LSB is set to a logic 1. Data from the register defined by the command byte then is sent by the PCA9557 (see Figure 8 and Figure 9). After a restart, the value of the register defined by the command byte matches the register being accessed when the restart occurred. Data is clocked into the register on the rising edge of the ACK clock pulse. There is no limitation on the number of data bytes received in one read transmission, but when the final byte is received, the bus master must not acknowledge the data. Figure 8. Read From Register <br/> A. This figure assumes the command byte has been previously programmed with 00h. B. Transfer of data can be stopped at any moment by a stop condition. When this occurs, data present at the last acknowledge phase is valid (output mode). Input data is lost. C. This figure eliminates the command byte transfer, a restart, and slave address call between the initial slave address call and actual data transfer from the P port (see Figure 8). Figure 9. Read Input Port Register 10 Submit Documentation Feedback Copyright © 2005–2008, Texas Instruments Incorporated Product Folder Link(s): PCA9557 |
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