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CMS3232LAH Datasheet(PDF) 5 Page - FIDELIX |
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CMS3232LAH Datasheet(HTML) 5 Page - FIDELIX |
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5 / 46 page  Rev0.2, Aug. 2006 CMS3232LAx-75Ex Pin Description Data Input/Output : Data bus I/O DQ No Connect - NC DQ Power: Provide isolated power to DQs for improved noise immunity. Supply V DDQ DQ Ground: Provide isolated ground to DQs for improved noise immunity. Supply V SSQ Power Supply: Voltage dependent on option. Supply V DD Ground. Supply V SS Address Inputs: A0–A10 are sampled during the ACTIVE command (row-address A0–A10) and READ/WRITE command (column-address A0–A7; with A10 defining auto precharge) to select one location out of the memory array in the respective bank. A10 is sampled during a PRECHARGE command to determine if all banks are to be precharged (A10 HIGH) or bank selected by BS (A10 LOW). The address inputs also provide the op-code during a LOAD MODE REGISTER command. Input A0-A10 Input/Output Mask: DQM is sampled HIGH and is an input mask signal for write accesses and an output enable signal for read accesses. Input data is masked during a WRITE cycle. The output buffers are placed in a High-Z state (two-clock latency) when during a READ cycle. DQM0 corresponds to DQ0 – DQ7, DQM1 corresponds to DQ8–DQ15, DQM2 corresponds to DQ16–DQ23, AND DQM3 corresponds to DQ24–DQ31. Input DQM0 ~ DQM3 Bank Address Input(s): BS define to which bank the ACTIVE, READ, WRITE or PRECHARGE command is being applied. These pins also provide the op-code during a LOAD MODE REGISTER command. Input BS Input Input Input Input Type /CAS, /RAS, /WE /CS CKE CLK Symbol Chip Select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when /CS is registered HIGH. /CS provides for external bank selection on systems with multiple banks. /CS is considered part of the command code. Command Inputs : /CAS, /RAS, and /WE (along with /CS) define the command being entered. Clock Enable: CKE activates(HIGH) and deactivates(LOW) the CLK signal. Deactivating the clock provides PRECHARGE POWER-DOWN and SELF REFRESH operation(all banks idle), ACTIVE POWER-DOWN(row active in any bank) or CLOCK SUSPEND operation(burst/access in progress). CKE is synchronous except after the device enters power-down and self refresh modes, where CKE becomes asynchronous until after exiting the same mode. The input buffers, including CLK, are disabled during power-down and self refresh modes, providing low standby power. CKE may be tied HIGH. Clock : CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers. Description |
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