8

5185D–SEEPR–1/08

AT34C02C

Figure 4-5.

Output Acknowledge

5. Device Addressing

The 2K EEPROM device requires an 8-bit device address word following a start condition to

enable the chip for a read or write operation (see Figure 8-1 on page 13).

The device address word consists of a mandatory one-zero sequence for the first four most-sig-

nificant bits (1010) for normal read and write operations and 0110 for writing to the write protect

register.

The next 3 bits are the A2, A1 and A0 device address bits for the AT34C02C EEPROM. These 3

bits must compare to their corresponding hard-wired input pins.

The eighth bit of the device address is the read/write operation select bit. A read operation is ini-

tiated if this bit is high and a write operation is initiated if this bit is low.

Upon a compare of the device address, the EEPROM will output a zero. If a compare is not

made, the chip will return to a standby state. The device will not acknowledge if the write protect

register has been programmed and the control code is 0110.

6. Write Operations

BYTE WRITE: A write operation requires an 8-bit data word address following the device

address word and acknowledgment. Upon receipt of this address, the EEPROM will again

respond with a zero and then clock in the first 8-bit data word. Following receipt of the 8-bit data

word, the EEPROM will output a zero and the addressing device, such as a microcontroller,

must terminate the write sequence with a stop condition. At this time the EEPROM enters an

write cycle and the EEPROM will not respond until the write is complete (see Figure 8-2 on page

13).

The device will acknowledge a write command, but not write the data, if the software or hard-

ware write protection has been enabled. The write cycle time must be observed even when the

write protection is enabled.

PAGE WRITE: The 2K device is capable of 16-byte page write.