9

5165E–SEEPR–8/08

AT25512

Protection Level. During an internal write cycle, all commands will be ignored except the RDSR

instruction.

A Write Instruction requires the following sequence. After the CS line is pulled low to select the

device, the Write op-code is transmitted via the SI line followed by the byte address and the data

(D7 – D0) to be programmed (see Table 3-6). Programming will start after the CS pin is brought

high. (The Low-to-High transition of the CS pin must occur during the SCK low time immediately

after clocking in the D0 (LSB) data bit.

The Ready/Busy status of the device can be determined by initiating a Read Status Register

(RDSR) Instruction. If Bit 0 = 1, the Write cycle is still in progress. If Bit 0 = 0, the Write cycle has

ended. Only the Read Status Register instruction is enabled during the Write programming

cycle.

The AT25512 is capable of a 128-byte Page Write operation. After each byte of data is received,

the seven low order address bits are internally incremented by one; the high order bits of the

address will remain constant. If more than 128 bytes of data are transmitted, the address coun-

ter will roll over and the previously written data will be overwritten. The AT25512 is automatically

returned to the write disable state at the completion of a Write cycle.

NOTE: If the device is not write enabled (WREN), the device will ignore the Write instruction

and will return to the standby state, when CS is brought high. A new CS falling edge is required

to re-initiate the serial communication.

Table 3-6.

Address Key

Address

AT25512