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ATA5423 Datasheet(PDF) 45 Page - ATMEL Corporation |
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ATA5423 Datasheet(HTML) 45 Page - ATMEL Corporation |
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45 / 100 page  45 4841D–WIRE–10/07 ATA5423/ATA5425/ATA5428/ATA5429 If the transceiver is in any active mode (IDLE, AUX, TX, RX, RX_Polling), an integrated debounce logic is active. If there is an event on pin Tn a debounce counter is set to 0 (T = 0) and started. The status is updated, an interrupt is issued and the debounce counter is stopped after reaching the counter value T = 8195 × T DCLK. An event on the same key input before reaching T = 8195 × T DCLK stops the debounce counter. An event on an other key input before reaching T = 8195 × T DCLK resets and restarts the debounce counter. While the debounce counter is running, the bits VSOUT_EN and CLK_ON in control register 3 are set to “1”. The interrupt is deleted after reading the status register or executing the command Delete_IRQ. If pin Tn is not used, it can be left open because of an internal pull-up resistor (typically 50 k Ω). Figure 7-3. Timing Flow Pin Tn, Status Bit STn IDLE Mode or AUX Mode or TX Mode or RX Polling Mode or RX Mode Stop debounce counter STn = 1 IRQ = 1 Stop debounce counter STn = 0 IRQ = 1 Stop debounce counter Tn = STn ? Pin Tn = 0 ? T = 0 Start debounce counter Event on Pin Tn ? Event on Pin Tn ? N N N N Y Y Y Y Y N T = 8195 × T ? |
Similar Part No. - ATA5423_07 |
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Similar Description - ATA5423_07 |
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