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SC1189 Datasheet(PDF) 7 Page - Semtech Corporation |
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SC1189 Datasheet(HTML) 7 Page - Semtech Corporation |
7 / 16 page 7 2007 Semtech Corp. www.semtech.com POWER MANAGEMENT SC1189 Careful attention to layout requirements are necessary for successful implementation of the SC1189 PWM control- ler. High currents switching at 200kHz are present in the application and their effect on ground plane voltage differ- entials must be understood and minimized. 1). The high power parts of the circuit should be laid out first. A ground plane should be used, the number and position of ground plane interruptions should be such as to not unnecessarily compromise ground plane integrity. Isolated or semi-isolated areas of the ground plane may be deliberately introduced to constrain ground currents to particular areas, for example the input capacitor and bot- tom FET ground. 2). The loop formed by the Input Capacitor(s) (Cin), the Top FET (Q1) and the Bottom FET (Q2) must be kept as small as possible. This loop contains all the high current, fast Layout Guidelines transition switching. Connections should be as wide and as short as possible to minimize loop inductance. Mini- mizing this loop area will a) reduce EMI, b) lower ground injection currents, resulting in electrically “cleaner” grounds for the rest of the system and c) minimize source ringing, resulting in more reliable gate switching signals. 3). The connection between the junction of Q1, Q2 and the output inductor should be a wide trace or copper re- gion. It should be as short as practical. Since this connec- tion has fast voltage transitions, keeping this connection short will minimize EMI. The connection between the out- put inductor and the sense resistor should be a wide trace or copper area, there are no fast voltage or current transi- tions in this connection and length is not so important, however adding unnecessary impedance will reduce effi- ciency. Vout 12V IN 3.3V Vo Lin1 Vo Lin2 5V L 5mOhm + Cout + Cin 10 Q2 0.1uF Q3 + Cout Lin1 2.32k Q4 + Cout Lin2 1.00k + Cin Lin SC1189 AGND 1 VCC 5 PWRGD 6 LDOEN 7 CS- 8 CS+ 9 PGNDH 10 DH 11 BSTH 15 EN 16 VOSENSE 17 VID25MV 18 VID3 19 VID2 20 VID1 21 VID0 22 DL 13 PGNDL 12 BSTL 14 GATE2 24 GATE1 2 LDOV 23 LDOS1 3 LDOS2 4 Q1 0.1uF Heavy lines indicate high current paths. Layout Diagram SC1189 |
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