SX1501I087TRT datasheet(8/34 Pages) SEMTECH

Part #	SX1501I087TRT

Description	4/8/16 Channel Low Voltage GPIO

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Manufacturer	SEMTECH [Semtech Corporation]

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ADVANCED COMMUNICATIONS & SENSING

Rev 7 – 2

nd Oct. 2008

www.semtech.com

8

SX1501/SX1502/SX1503

4/8/16 Channel Low Voltage GPIO

Symbol

Description

Conditions

Min

Typ

Max

Unit

tIR

Interrupt reset timing

From RegInterruptSource

clearing

-

2

µs

NRESET (Input/Output)

VOL

Low level output voltage

-

0.3

V

VDDM >= 2V

-

12

IOLM

Low level output sink current

VDDM < 2V

-

6

mA

VIHMR

High level input voltage

-

0.7*

VDDM

-

5.5

V

VILM

Low level input voltage

-

-0.4

-

0.3*

VDDM

V

VHYSM

Hysteresis of Schmitt trigger

-

0.1*

VDDM

-

V

ILEAK

Input leakage current

-

-1.5

-

1.5

µA

CI

Input capacitance

-

10

pF

VPOR

Power-On-Reset voltage

Cf. Figure 7

0.7

-

0.9

V

VDROPH High brown-out voltage

Cf. Figure 7

-

VDDM-1

-

V

VDROPL Low brown-out voltage

Cf. Figure 7

-

0.2

-

V

tRESET

Reset time

Cf. Figure 7

0.6

-

7

ms

tPULSE

Reset pulse from host uC

Cf. Figure 7

300

-

ns

ADDR (Input)

VIHMA

High level input voltage

-

0.7*

VDDM

-

VDDM

+0.3

V

VILM

Low level input voltage

-

-0.4

-

0.3*

VDDM

V

VHYSM

Hysteresis of Schmitt trigger

-

0.1*

VDDM

-

V

ILEAK

Input leakage current

-

-1.5

-

1.5

µA

CI

Input capacitance

-

10

pF

SCL (Input) and SDA (Input/Output)

(3)

Interface complies with slave F/S mode I

2C interface as described by Philips I2C specification version 2.1

dated January, 2000. Please refer to that document for more detailed I

2C specifications.

VOL

Low level output voltage

-

0.3

V

VDDM >= 2V

-

12

IOLM

Low level output sink current

VDDM < 2V

-

6

mA

VIHMR

High level input voltage

-

0.7*

VDDM

-

5.5

V

VILM

Low level input voltage

-

-0.4

-

0.3*

VDDM

V

fSCL

SCL clock frequency

-

0

-

400

kHz

tHD;STA

Hold time (repeated) START

condition

-

0.6

-

µs

tLOW

LOW period of the SCL clock

-

1.3

-

µs

VDDM >= 1.3V

0.6

-

tHIGH

HIGH period of the SCL clock

VDDM < 1.3V

1

-

µs

tSU;STA

Set-up time for a repeated

START condition

-

0.6

-

µs

tHD;DAT

Data hold time

-

0

(4)

-

0.9

(5)

µs

tSU;DAT

Data set-up time

-

100

(6)

-

tr

Rise time of both SDA and

SCL signals

-

20+0.1Cb

(7)

-

300

ns

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