Asynchronous Registered EPLD
fax id: 6016
CY7C331
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
January 1989 – Revised December 1992
1CY7C331
Features
• Twelve I/O macrocells each having:
— One state flip-flop with an XOR sum-of-products
input
— One feedback flip-flop with input coming from the
I/O pin
— Independent (product term) set, reset, and clock in-
puts on all registers
— Asynchronous bypass capability on all registers un-
der product term control (r = s = 1)
— Global or local output enable on three-state I/O
— Feedback from either register to the array
• 192 product terms with variable distribution to macro-
cells
• 13 inputs, 12 feedback I/O pins, plus 6 shared I/O mac-
rocell feedbacks for a total of 31 true and complemen-
tary inputs
• High speed: 20 ns maximum tPD
• Security bit
• Space-saving 28-pin slim-line DIP package; also avail-
able in 28-pin PLCC
• Low power
— 90 mA typical ICC quiescent
— 180 mA ICC maximum
— UV-erasable and reprogrammable
— Programming and operation 100% testable
Functional Description
The CY7C331 is the most versatile PLD available for asyn-
chronous designs. Central resources include twelve full D-type
flip-flops with separate set, reset, and clock capability. For in-
creased utility, XOR gates are provided at the D-inputs and the
product term allocation per flip-flop is variably distributed.
I/O Resources
Pins 1 through 7 and 9 through 14 serve as array inputs; pin
14 may also be used as a global output enable for the I/O
macrocell three-state outputs. Pins 15 through 20 and 23
through 28 are connected to I/O macrocells and may be man-
aged as inputs or outputs depending on the configuration and
the macrocell OE terms.
Logic Block Diagram
C331–1
14
13
12
11
10
9
7
6
5
4
3
2
1
8
15
16
17
18
19
20
23
24
25
26
27
28
22
21
GND
VCC
PROGRAMMABLE AND ARRAY
(192x62)
10
6
8
8
12
4
6
10
4
12
8
8
I/O11
I/O10
I/O9
I/O8
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
GND
I6
OE/I12
I11
I10
I9
I8
I7
I5
I4
I3
I2
I1
I0
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