CY7C335-66HC datasheet(2/17 Pages) CYPRESS

Part #	CY7C335-66HC

Description	Universal Synchronous EPLD

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Manufacturer	CYPRESS [Cypress Semiconductor]

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CY7C335

2

Architecture Configuration Bits

The architecture configuration bits are used to program the

multiplexers. The function of the architecture bits is outlined in

Table 1.

Pin Configurations

Top View

PLCC

LCC

Top View

5

6

7

8

9

10

11

4 3 2

282726

12131415161718

25

24

23

22

21

20

19

25

24

23

22

21

20

19

5

6

7

8

9

10

11

121314 1516 1718

4 3 2

2827 26

1

C335–2

C335–3

I3

I4

I5

I6

I7

I8

VSS

I3

I4

I5

I6

I7

I8

VSS

I/O3

I/O4

I/O5

VCC

VSS

I/O6

I/O7

I/O3

I/O4

I/O5

VCC

VSS

I/O6

I/O7

Selection Guide

CY7C335–100

CY7C335–83

CY7C335–66

CY7C335–50

Maximum Operating

Frequency (MHz)

Commercial

100

83.3

66.6

50

Military

83.3

66.6

50

ICC1 (mA)

Commercial

140

Military

160

Table 1. Architecture Configuration Bits

Architecture

Configuration Bit

Number of Bits

Value

Function

C0

Output Enable

Select MUX

12 Bits, 1 Per

I/O Macrocell

0—Virgin State

Output Enable Controlled by Product Term

1—Programmed

Output Enable Controlled by Pin 14

C1

State Register

Feed Back MUX

12 Bits, 1 Per

I/O Macrocell

0—Virgin State

State Register Output is Fed Back to Input Array

1—Programmed

I/O Macrocell is Configured as an Input and

Output of Input Path is Fed to Array

C2

I/O Macrocell

Input Register

Clock Select

MUX

12 Bits, 1 Per

I/O Macrocell

0—Virgin State

ICLK1 Controls the Input Register I/O Macrocell

Input Register Clock Input

1—Programmed

ICLK2 Controls the Input Register I/O Macrocell

Input Register Clock Input

C3

Input Register

Bypass MUX—

I/O Macrocell

12 Bits, 1 Per

I/O Macrocell

0—Virgin State

Selects Input to Feedback MUX from Input

Register

1—Programmed

Selects Input to Feedback MUX from I/O pin

C4

Output Register

Bypass MUX

12 Bits, 1 Per

I/O Macrocell

0—Virgin State

Selects Output from the State Register

1—Programmed

Selects Output from the Array, Bypassing the

State Register

C5

State Clock MUX

16 Bits, 1 Per I/O

Macrocell and 1 Per

Hidden Macrocell

0—Virgin State

State Clock 1 Controls the State Register

1—Programmed

State Clock 2 Controls the State Register

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