CY7C331
6
tIRW
Input Register Reset Width[4, 8]
35
40
ns
tIRR
Input Register Reset Recovery Time[4, 8]
35
40
ns
tIAS
Input to Input Register Asynchronous Set Delay[8]
35
40
ns
tISW
Input Register Set Width[4, 8]
35
40
ns
tISR
Input Register Set Recovery Time[4, 8]
35
40
ns
tWH
Input and Output Clock Width HIGH[8, 9, 10]
12
15
ns
tWL
Input and Output Clock Width LOW[8, 9, 10]
12
15
ns
fMAX1
Maximum Frequency with Feedback in Input Registered Mode
(1/(tICO + tIS))
[11]
27.0
23.8
MHz
fMAX2
Maximum Frequency Data Path in Input Registered Mode (Lowest
of 1/tICO, 1/(tWH + tWL), or 1/(tIS + tIH)
[8]
28.5
25.0
MHz
tIOH–tIH33X
Output Data Stable from Input Clock Minus Input Register Input
Hold Time for 7C335[12, 13]
0
0
ns
tCO
Output Register Clock to Output Delay[9]
20
25
ns
tOH
Output Data Stable Time from Output Clock[9]
3
3
ns
tS
Output Register Input Set-Up Time to Output Clock[9]
12
12
ns
tH
Output Register Input Hold Time from Output Clock[9]
8
8
ns
tOAR
Input to Output Register Asynchronous Reset Delay[9]
20
25
ns
tORW
Output Register Reset Width[9]
20
25
ns
tORR
Output Register Reset Recovery Time[9]
20
25
ns
tOAS
Input to Output Register Asynchronous Set Delay[9]
20
25
ns
tOSW
Output Register Set Width[9]
20
25
ns
tOSR
Output Register Set Recovery Time[9]
20
25
ns
tEA
Input to Output Enable Delay[14, 15]
25
25
ns
tER
Input to Output Disable Delay[14, 15]
25
25
ns
tPZX
Pin 14 to Output Enable Delay[14, 15]
20
20
ns
tPXZ
Pin 14 to Output Disable Delay[14, 15]
20
20
ns
fMAX3
Maximum Frequency with Feedback in Output Registered Mode
(1/(tCO + tS))
[16, 17]
31.2
27.0
MHz
fMAX4
Maximum Frequency Data Path in Output Registered Mode (Lowest
of 1/tCO, 1/(tWH + tWL), or 1/(tS + tH))
[9]
41.6
33.3
MHz
tOH–tIH33X
Output Data Stable from Output Clock Minus Input
Register Input Hold Time for 7C335[13, 18]
0
0
ns
fMAX5
Maximum Frequency Pipelined Mode[10, 17]
35.0
30.0
MHz
Notes:
7.
Refer to
Figure 3, configuration 1.
8.
Refer to
Figure 3, configuration 2.
9.
Refer to
Figure 3, configuration 3.
10. Refer to
Figure 3, configuration 6.
11. Refer to
Figure 3, configuration 7.
12. Refer to
Figure 3, configuration 9.
13. This specification is intended to guarantee interface compatibility of the other members of the CY7C330 family with the CY7C331. This specification is met
for the devices noted operating at the same ambient temperature and at the same power supply voltage. These parameters are tested periodically by sampling
of production product.
14. Part (a) of AC Test Loads and Waveforms used for all parameters except tPZXI, tPXZI, tPZX, and tPXZ, which use part (b). Part (c) shows the test waveforms and
measurement levels.
15. Refer to
Figure 3, configuration 4.
16. Refer to
Figure 3, configuration 8.
17. This specification is intended to guarantee that a state machine configuration created with internal or external feedback can be operated with output register
and input register clocks controlled by the same source. These parameters are tested by periodic sampling of production product.
Switching Characteristics Over the Operating Range[2] (continued)
Parameter
Description
Commercial
–20
–25
Min.
Max.
Min.
Max.
Unit