CY7C331
7
Switching Characteristics Over the Operating Range[2] (continued)
Parameter
Description
Military
–25
–30
–40
Min.
Max.
Min.
Max.
Min.
Max.
Unit
tPD
Input to Output Propagation Delay[7]
25
30
40
ns
tICO
Input Register Clock to Output Delay[4, 8]
45
50
65
ns
tIOH
Output Data Stable Time from Input Clock[4, 8]
5
5
5
ns
tIS
Input or Feedback Set-Up Time to Input Register Clock[8]
5
5
5
ns
tIH
Input Register Hold Time from Input Clock[4, 8]
13
15
20
ns
tIAR
Input to Input Register Asynchronous Reset Delay[4, 8]
45
50
65
ns
tIRW
Input Register Reset Width[8]
45
50
65
ns
tIRR
Input Register Reset Recovery Time[8]
45
50
65
ns
tIAS
Input to Input Register Asynchronous Set Delay[8]
45
50
65
ns
tISW
Input Register Set Width[8]
45
50
65
ns
tISR
Input Register Set Recovery Time[8]
45
50
65
ns
tWH
Input and Output Clock Width High[8, 9, 10]
15
20
25
ns
tWL
Input and Output Clock Width Low[8, 9, 10]
15
20
25
ns
fMAX1
Maximum frequency with Feedback in Input Registered
Mode (1/(tICO + tIS))
[11]
20.0
18.1
14.2
MHz
fMAX2
Maximum frequency Data Path in Input Registered Mode
(Lowest of 1/tICO, 1/(tWH + tWL), or 1/(tIS + tIH)
[8]
22.2
20.0
15.3
MHz
tIOH–tIH33X
Output Data Stable from Input Clock Minus Input Register
Input Hold Time for 7C335[12, 13]
0
0
0
ns
tCO
Output Register Clock to Output Delay[9]
25
30
40
ns
tOH
Output Data Stable Time from Output Clock[9]
3
3
3
ns
tS
Output Register Input Set-Up Time to Output Clock[9]
15
15
20
ns
tH
Output Register Input Hold Time from Output Clock[9]
10
10
12
ns
tOAR
Input to Output Register Asynchronous Reset Delay[9]
25
30
40
ns
tORW
Output Register Reset Width[9]
25
30
40
ns
tORR
Output Register Reset Recovery Time[9]
25
30
40
ns
tOAS
Input to Output Register Asynchronous Set Delay[9]
25
30
40
ns
tOSW
Output Register Set Width[9]
25
30
40
ns
tOSR
Output Register Set Recovery Time[9]
25
30
40
ns
tEA
Input to Output Enable Delay[14, 15]
25
30
40
ns
tER
Input to Output Disable Delay[14, 15]
25
30
40
ns
tPZX
Pin 14 to Output Enable Delay[14, 15]
20
25
35
ns
tPXZ
Pin 14 to Output Disable Delay[14, 15]
20
25
35
ns
fMAX3
Maximum Frequency with Feedback in Output Registered
Mode )1/(tCO + tS)
[16, 17]
25.0
22.2
16.6
MHz
fMAX4
Maximum Frequency Data Path in Output Registered
Mode (Lowest of 1/tCO, 1/(tWH + tWL), or 1/(tS + tH)
[9]
33.3
25.0
20.0
MHz
tOH–tIH33X
Output Data Stable from Output Clock Minus Input Regis-
ter Input Hold Time for 7C335[13, 18]
0
0
0
ns
fMAX5
Maximum Frequency Pipelined Mode[10, 17]
28.0
23.5
18.5
MHz
Note:
18. Refer to
Figure 3, configuration 10.
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