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ACS8525A Datasheet(PDF) 22 Page - Semtech Corporation |
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ACS8525A Datasheet(HTML) 22 Page - Semtech Corporation |
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22 / 112 page  ACS8525A LC/P ADVANCED COMMS & SENSING FINAL DATASHEET Revision 1.00/September 2007 © Semtech Corp. Page 22 www.semtech.com Outputs The ACS8525A delivers four output signals on the following ports: Two clocks, one each on ports Output O1 and Output O2; and two Sync signals, on ports FrSync and MFrSync. Output O1 and Output O2 are independent of each other and are individually selectable. Output 01 is a differential port (pins O1POS and O1NEG), and can be selected PECL or LVDS. Output O2 (pin O2) and the Sync outputs are TTL/CMOS. The two Sync outputs, FrSync (8 kHz) and MFrSync (2 kHz), are derived from DPLL1. PECL/LVDS Output Port Selection The choice of PECL or LVDS compatibility for Output 01 is programmed via the cnfg_differential_output register, Reg. 3A. Output Frequency Selection and PLL Configuration The output frequency at many of the outputs is controlled by a number of inter-dependent parameters (refer to “PLL Architecture” on page 14). The frequencies of the output clocks are selectable from a range of pre-defined spot frequencies/port technologies, as defined in Tables 6 and 7. Outputs O1 & O2 Frequency Configuration Steps The output frequency selection is performed in the following steps: 6. Refer to Table 8, Frequency Divider Look-up, to choose a set of output frequencies. 7. Refer to the Table 8 to determine the required APLL frequency to support the frequency set. 8. Refer to Table 9, APLL1 Frequencies, and Table 10, APLL2 Frequencies, to determine in what mode DPLL1 and DPLL2 need to be configured, considering the output jitter level. 9. Refer to Table 11, O1 and O2 Output Frequency Selection, and the column headings in Table 8, Frequency Divider Look-up, to select the appropriate frequency from either of the APLLs on each output as required. Note...1.544 MHz/2.048 MHz are shown for SONET/SDH respectively. Pin SONSDHB controls default, when High SONET is default Table 6 Output Reference Source Selection Table Port Name Output Port Technology Frequencies Supported Output O1 LVDS/PECL (LVDS default) Frequency selection as per Table 7 and Table 11 Output O2 TTL/CMOS FrSync TTL/CMOS FrSync, 8 kHz programmable pulse width and polarity, see Reg. 7A. MFrSync TTL/CMOS MFrSync, 2 kHz programmable pulse width and polarity, see Reg. 7A. Table 7 Output Frequency Selection Frequency (MHz, unless stated otherwise) DPLL1 Mode DPLL2 Mode APLL2 Input Mux Jitter Level (Typ) rms (ps) p-p (ns) 2 kHz 77.76 MHz Analog - - 60 0.6 2 kHz Any digital feedback mode - - 1400 5 8 kHz 77.76 MHz Analog - - 60 0.6 8 kHz Any digital feedback mode - - 1400 5 |
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