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ACS8525 Datasheet(PDF) 88 Page - Semtech Corporation |
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ACS8525 Datasheet(HTML) 88 Page - Semtech Corporation |
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88 / 112 page  ADVANCED COMMUNICATIONS FINAL DATASHEET Revision 3.01/August 2005 © Semtech Corp. Page 88 www.semtech.com ACS8525 LC/P [5:0] PBO_phase_offset Each time a Phase Build-out event is triggered, there is an uncertainty of up to 5 ns introduced which translates to a phase hit on the output. The mean error over a large number of events is designed to be zero. This register can be used to introduce a fixed offset into each PBO event. This will have the effect of moving the mean error positive or negative in time. - The value in this register is a 6-bit 2’s complement number. The value multiplied by 0.101 gives the programmed offset in nanoseconds. Values greater than +1.4 ns or less than -1.4 ns should NOT be used as they may cause internal mathematical errors. Address (hex): 73 Register Name cnfg_phase_loss_fine_limit Description (R/W) Register to configure some of the parameters of the DPLL phase detectors. Default Value 1010 0010 Bit 7Bit 6 Bit 5Bit 4 Bit 3 Bit 2Bit 1Bit 0 fine_limit_en noact_ph_loss narrow_en phase_loss_fine_limit Bit No. Description Bit Value Value Description 7 fine_limit_en Register bit to enable the phase_loss_fine_limit Bits [2:0]. When disabled, phase lock/loss is determined by the other means within the device. This must be disabled when multi-UI jitter tolerance is required, see Reg. 74, cnfg_phase_loss_course_limit. 0 1 Phase loss indication only triggered by other means. Phase loss triggered when phase error exceeds the limit programmed in phase_loss_fine_limit, Bits [2:0]. 6 noact_ph_loss The DPLL detects that an input has failed very rapidly. Normally, when the DPLL detects this condition, it does not consider phase lock to be lost and will phase lock to the nearest edge (±180º) when a source becomes available again, hence giving tolerance to missing cycles. If phase loss is indicated, then frequency and phase locking is instigated (±360º locking). This bit can be used to force the DPLL to indicate phase loss immediately when no activity is detected. 0 1 No activity on reference does not trigger phase lost indication. No activity triggers phase lost indication. Address (hex): 72 (cont...) Register Name cnfg_PBO_phase_offset Description (R/W) Register to offset the mean time error of Phase Build-out events. Default Value 0000 0000 Bit 7Bit 6 Bit 5Bit 4 Bit 3 Bit 2Bit 1Bit 0 PBO_phase_offset Bit No. Description Bit Value Value Description |
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