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ACS8522A Datasheet(PDF) 29 Page - Semtech Corporation |
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ACS8522A Datasheet(HTML) 29 Page - Semtech Corporation |
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29 / 118 page  ACS8522A SETS LITE ADVANCED COMMS & SENSING FINAL DATASHEET Revision 1.00/September 2007 © Semtech Corp. Page 29 www.semtech.com Figure 10 PLL Block Diagram The T4 output APLL block is also for multiplying and filtering. The input to the T4 output APLL can come either from the T4 forward DFS block or from the T0 path. The input to the T4 output APLL can be programmed to be one of the following: (a) Output from the T4 forward DFS block (12E1, 24DS1, 16E1, 16DS1, E3, DS3, OC-N), (b) 12E1 from T0, (c) 16E1 from T0, (d) 24DS1 from T0, (e) 16DS1 from T0. The frequency generated from the T4 output APLL block is four times its input frequency i.e. 311.04 MHz when used with a 77.76 MHz input. The T4 output APLL is subsequently divided by 2, 4, 8, 12, 16, 48 and 64 and these are available at the O1 to O4 outputs. The outputs O1 to O4 are driven from either the T4 or the T0 path. The FrSync and MFrSync outputs are always generated from the T0 path. Reg.7A bit 7 selects whether the source of the 2 kHz and 8 kHz outputs available from O1 to O4 is derived from either the T0 or the T4 paths. Output Frequency Configuration Steps The output frequency selection is performed in the following steps: 1. Does the application require the use of the T4 path as an independent PLL path or not. If not, then the T4 path can be utilized to produce extra frequencies locked to the T0 path. 2. Refer to Table 13, Frequency Divider Look-up, to choose a set of output frequencies- one for each path, T4 and T0. Only one set of frequencies can be generated simultaneously from each path. 3. Refer to the Table 13 to determine the required APLL frequency to support the frequency set. 4. Refer to Table 14, T0 APLL Frequencies, and Table 15, T4 APLL Frequencies, to determine what mode the T0 and T4 paths need to be configured in, considering the output jitter level. 5. Refer to Table 16, O1 to O4 Output Frequency Selection, and the column headings in Table 13, Frequency Divider Look-up, to select the appropriate frequency from either of the APLLs on each output as required. PFD and Loop Filter Forward DFS Feedback DFS F8522D_017BLOCKDIA_01 O1, O2 O3, O4 O1, O2 O3, O4 O1, O2 O3, O4 FrSync MFrSync PFD and Loop Filter Feedback DFS 77M Forward DFS 77M Output DFS LF Output DFS T4 Output APLL T4 Output Dividers T0 Output APLL T0 Feedback APLL T0 Output Dividers 1 0 0 1 0 1 1 1 0 0 T4 DPLL T0 DPLL Analog Reference Input SEC1 SEC2 SEC3 SEC4 Reference Input SEC1 SEC2 SEC3 SEC4 T4_Dig_Feedback T0_DPLL_Freq T4_APLL_for_T0 Lock_T4_to_T0 Control T4_DPLL_Frequency Sts_Current_Phase Sts_Current_Phase 8 kHz T0_DPLL_Frequency Control T0_DPLL_Frequency Control PBO Phase Offset Locking Frequency Locking Frequency T4 T0 0 1 0 1 |
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