ACS8522A datasheet(10/118 Pages) SEMTECH

Part #	ACS8522A

Description	Synchronous Equipment Timing Source for Stratum 3/4E/4 and SMC Systems

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Manufacturer	SEMTECH [Semtech Corporation]

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ACS8522A SETS LITE

ADVANCED COMMS & SENSING

FINAL

DATASHEET

Revision 1.00/September 2007 © Semtech Corp.

Page 10

www.semtech.com

DivN Mode

In DivN mode, the divider parameters are set manually by

configuration (Bit 7 of the cnfg_ref_source_frequency

register), but must be set so that the frequency after

division is 8 kHz. The DivN function is defined as:

DivN = “Divide by N+ 1”, i.e. it is the dividing factor used

for the division of the input frequency, and has a value of

(N+1) where N is an integer from 1 to 12499 inclusive.

Therefore, in DivN mode the input frequency can be

divided by any integer value between 2 to 12500.

Consequently, any input frequency which is a multiple of

8 kHz, between 8 kHz to 100 MHz, can be supported by

using DivN mode.

Note...Any reference input can be set to use DivN

independently of the frequencies and configurations of the

other inputs. However only one value of N is allowed, so all

inputs with DivN selected must be running at the same

frequency.

DivN Examples

(a) To lock to 2.000 MHz:

(i)

Set the cnfg_ref_source_frequency register to

10XX0000 (binary) to enable DivN, and set the

frequency to 8 kHz - the frequency required after

division. (XX = “Leaky Bucket” ID for this input).

(ii) To achieve 8 kHz, the 2 MHz input must be

divided by 250. So, if DivN = 250 = (N + 1)

then N must be set to 249. This is done by writing

F9 hex (249 decimal) to the DivN register pair

Reg. 46/47.

(b) To lock to 10.000 MHz:

(i)

The cnfg_ref_source_frequency register is set to

10XX0000 (binary) to set the DivN and the

frequency to 8 kHz, the post-division frequency.

(XX = “Leaky Bucket” ID for this input).

(ii) To achieve 8 kHz, the 10 MHz input must be

divided by 1,250. So, if DivN, = 250 = (N+1)

then N must be set to 1,249. This is done by

writing 4E1 hex (1,249 decimal) to the DivN

register pair Reg. 46/47.

Clock Quality Monitoring

Clock quality is monitored and used to modify the priority

tables. The following parameters are monitored:

1. Activity (toggling).

2. Frequency (this monitoring is only performed when

there is no irregular operation of the clock or loss of

clock condition).

Any reference source that suffers a loss-of-activity or

clock-out-of-band condition will be declared as

unavailable.

Clock quality monitoring is a continuous process which is

used to identify clock problems. There is a difference in

dynamics between the selected clock and the other

reference clocks. Anomalies occurring on non-selected

reference sources affect only that source's suitability for

selection, whereas anomalies occurring on the selected

clock could have a detrimental impact on the accuracy of

the output clock.

Anomalies detected by the activity detector are integrated

in a Leaky Bucket Accumulator. Occasional anomalies do

not cause the Accumulator to cross the alarm setting

threshold, so the selected reference source is retained.

Persistent anomalies cause the alarm setting threshold to

be crossed and result in the selected reference source

being rejected.

Anomalies on the currently locked-to input reference

clock, whether affecting signal purity or signal frequency,

could induce jitter or frequency offsets in the output clock,

leading to anomalous behavior. Anomalies on the

selected clock, therefore, have to be detected as they

occur and the phase locked loop must be temporarily

isolated until the clock is once again pure. The clock

monitoring process cannot be used for this because the

high degree of accuracy required dictates that the

process be slow. To achieve the immediacy required by

the phase locked loop requires an alternative

mechanism.

The phase locked loop itself contains a fast activity

detector such that within approximately two missing input

clock cycles, a no-activity flag is raised and the DPLL is

frozen in Holdover mode. This flag can also be read as the

main_ref_failed bit (from Reg. 06, Bit 6) and can be set to

indicate a phase lost state by enabling Reg. 73, Bit 6. With

the DPLL in Holdover mode it is isolated from further

disturbances. If the input becomes available again before

the activity or frequency monitor rejection alarms have

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