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ACS8522A Datasheet(PDF) 41 Page - Semtech Corporation |
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ACS8522A Datasheet(HTML) 41 Page - Semtech Corporation |
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41 / 118 page  ACS8522A SETS LITE ADVANCED COMMS & SENSING FINAL DATASHEET Revision 1.00/September 2007 © Semtech Corp. Page 41 www.semtech.com Each Register, or register group, is described in the following Register Map (Table 20) and subsequent Register Description Tables. Register Organization The ACS8522A SETS LITE uses a total of 95 eight-bit register locations, identified by a Register Name and corresponding hexadecimal Register Address. They are presented here in ascending order of Reg. address. and each Register is organized with the most-significant bit positioned in the left-most bit, and bit significance decreasing towards the right-most bit. Some registers carry several individual data fields of various sizes, from single-bit values (e.g. flags) upwards. Several data fields are spread across multiple registers, as shown in the Register Map, Table 20.Shaded areas in the map are “don’t care” and writing either 0 or 1 to them will not affect any function of the device.Bits labelled “Set to 0” or “Set to 1” must be set as stated during initialization of the device, either following power- up, or after a power-on reset (POR). Failure to correctly set these bits may result in the device operating in an unexpected way. CAUTION! Do not write to any undefined register addresses as this may cause the device to operate in a test mode. If an undefined register has been inadvertently addressed, the device should be reset to ensure the undefined registers are at default values. Multi-word Registers For multi-word registers (e.g. Reg. 70 and 71), all the words have to be written to their separate addresses, and without any other access taking place, before their combined value can take effect. If the sequence is interrupted the sequence of writes will be ignored. Reading a multi-word address freezes the other address words of a multi-word address so that the bytes all correspond to the same complete word. Register Access Most registers are of one of two types, configuration registers or status registers, the exceptions being the chip_id and chip_revision registers. Configuration registers may be written to or read from at any time (the complete 8-bit register must be written, even if only one bit is being modified). All status registers may be read at any time and, in some status registers (such as the sts_interrupts register), any individual data field may be cleared by writing a 1 into each bit of the field (writing a 0 value into a bit will not affect the value of the bit). Configuration Registers Each configuration register reverts to a default value on power-up or following a reset. Most default values are fixed, but some can be pin-set. All configuration registers can be read out over the serial port. Status Registers The Status Registers contain readable registers. They may all be read from outside the chip but are not writeable from outside the chip (except for a clearing operation). All status registers are read via shadow registers to avoid data hits due to dynamic operation. Interrupt Enable and Clear Interrupt requests are flagged on pin INTREQ; the active state (High or Low) is programmable and the pin can either be driven, or set to high impedance when non- active (Reg 7D refers). Bits in the interrupt status register are set (High) by the following conditions; 1. Any reference source becoming valid or going invalid. 2. A change in the operating state (e.g. Locked, Holdover 3. A brief loss of the currently selected reference source. All interrupt sources, see Reg. 05, Reg. 06 and Reg. 08, are maskable via the mask register, each one being enabled by writing a 1 to the appropriate bit. Any unmasked bit set in the interrupt status register will cause the interrupt request pin to be asserted.All interrupts are cleared by writing a 1 to the bit(s) to be cleared in the status register. When all pending unmasked interrupts are cleared the interrupt pin will go inactive. Defaults Each Register is given a defined default value at reset and these are listed in the Map and Description Tables. However, some read-only status registers may not necessarily show the same default values after reset as those given in the tables. This is because they reflect the status of the device which may have changed in the time it takes to carry out the read, or through reasons of configuration. In the same way, the default values given for shaded areas could also take different values to those stated. Register Map |
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