ACS8520T datasheet(92/150 Pages) SEMTECH

Part #	ACS8520T

Description	Synchronous Equipment Timing Source for Stratum 3/4E/4 and SMC Systems

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ADVANCED COMMUNICATIONS

FINAL

DATASHEET

Revision 3.02/October 2005 © Semtech Corp.

Page 92

www.semtech.com

ACS8520 SETS

Address (hex):

41

Register Name cnfg_DPLL_freq_limit

[7:0]

Description

(R/W) Bits [7:0] of the DPLL

frequency limit register.

Default Value

0111 0110

Bit 7Bit 6

Bit 5Bit 4

Bit 3

Bit 2Bit 1Bit 0

DPLL_freq_limit_value[7:0]

Bit No.

Description

Bit Value

Value Description

[7:0]

DPLL_freq_limit_value[7:0]

This register defines the extent of frequency offset

to which either the T0 or the T4 DPLL will track a

source before limiting- i.e. it represents the pull-in

range of the DPLLs. The offset of the device is

determined by the frequency offset of the DPLL

when compared to the offset of the external crystal

oscillator clocking the device. If the oscillator is

calibrated using cnfg_nominal_frequency Reg. 3C

and 3D, then this calibration is automatically taken

into account. The DPLL frequency limit limits the

offset of the DPLL when compared to the calibrated

oscillator frequency.

-

In order to calculate the frequency limit in ppm,

Bits [1:0] of Reg. 42 and Bits [7:0] of Reg. 41 need

to be concatenated. This value is a unsigned integer

and represents limit both positive and negative in

ppm. The value multiplied by 0.078 will give the

value in ppm.

Address (hex):

42

Register Name cnfg_DPLL_freq_limit

[9:8]

Description

(R/W) Bits [9:8] of the DPLL

frequency limit register.

Default Value

0000 0000

Bit 7Bit 6

Bit 5Bit 4

Bit 3

Bit 2Bit 1Bit 0

DPLL_freq_limit_value[9:8]

Bit No.

Description

Bit Value

Value Description

[7:2]

Not used.

-

[1:0]

DPLL_freq_limit_value[9:8]

-

See Reg. 41 (cnfg_DPLL_freq_limit) for details.

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