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ACS8522 Datasheet(PDF) 1 Page - Semtech Corporation

Part No. ACS8522
Description  Synchronous Equipment Timing Source for Stratum 3/4E/4 and SMC Systems
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Maker  SEMTECH [Semtech Corporation]
Homepage  http://www.semtech.com
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ACS8522 Datasheet(HTML) 1 Page - Semtech Corporation

 
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Revision 5/November 2006 © Semtech Corp.
Page 1
www.semtech.com
ACS8522 SETS LITE
ADVANCED COMMUNICATIONS
FINAL
Synchronous Equipment Timing Source for
Stratum 3/4E/4 and SMC Systems
ADVANCED COMMUNICATIONS
FINAL
DATASHEET
The ACS8522 is a highly integrated, single-chip solution
for the Synchronous Equipment Timing Source (SETS)
function in a SONET or SDH Network Element. The device
generates SONET or SDH Equipment Clocks (SEC) and
Frame Synchronization clocks. The ACS8522 is fully
compliant with the required international specifications
and standards.
The device supports Free-run, Locked and Holdover
modes, with mode selection controlled either
automatically by an internal state machine or forced by
register configuration.
The ACS8522 accepts up to four independent input SEC
reference clock sources from Recovered Line Clock, PDH
network, and Node Synchronization. The ACS8522
generates independent SEC and BITS clocks, an 8 kHz
Frame Synchronization clock and a 2 kHz Multi-Frame
Synchronization clock, both with programmable pulse
width and polarity.
The ACS8522 includes a Serial Port, which can be SPI
compatible, providing access to the configuration and
status registers for device setup.
The ACS8522 supports IEEE 1149.1[5] JTAG boundary
scan.
The User can choose between OCXO or TCXO to define the
Stratum and/or Holdover performance required.
Suitable for Stratum 3, 4E, 4 and SONET Minimum
Clock (SMC) or SONET/SDH Equipment Clock (SEC)
applications (to Telcordia 1244-CORE[19] Stratum 3
and GR-253[17], and ITU-T G.813[11] Options
Ι and ΙΙ
specifications)
Accepts four individual input reference clocks, all with
robust input clock source quality monitoring
Simultaneously generates four output clocks, plus two
Sync pulse outputs
Absolute Holdover accuracy better than 3 x 10-10
(manual), 7.5 x 10-14 (instantaneous); Holdover
stability defined by choice of external XO
Programmable PLL bandwidth, for wander and jitter
tracking/attenuation, 0.1 Hz to 70 Hz in 10 steps
Automatic hit-less source switchover on loss of input
Serial SPI compatible interface
Output phase adjustment in 6 ps steps up to ±200 ns
IEEE 1149.1[5] JTAG Boundary Scan
Available in LQFP 64-pin package
Single 3.3 V operation. 5 V tolerant
Lead (Pb)-free version available (ACS8522T), RoHS
and WEEE compliant.
Figure 1 Block Diagram of the ACS8522 SETS LITE
Block Diagram
Description
Features
IEEE
1149.1
JTAG
Input
Port
Monitors
and
Selection
Control
4 x SEC
Optional
Divider, 1/n
n = 1 to 214
Optional
Divider, 1/n
n = 1 to 214
PFD
Digital
Loop
Filter
Chip
Clock
Generator
DTO
TCK
TDI
TMS
TRST
TDO
F8522P_001BLOCKDIA_04
T4 DPLL
Selector
T0 DPLL
Selector
PFD
Digital
Loop
Filter
DTO
T4 Output
APLL
Frequency
Dividers
T0 Output
APLL
Frequency
Dividers
T0 Feedback
APLL
FrSync
&
MFrSync
O1
to
O4
Output O1: PECL/LVDS
Outputs O2 - 04: TTL
Programmable;
E1/DS1 (2.048/
1.544 MHz)
and frequency
multiples:
1.5 x, 2 x, 3 x
4 x, 6 x, 12 x
16 x and 24 x
E3/DS3
2 kHz
8 kHz
and OC-N* rates
OC-N* rates =
OC-1 51.84 MHz
OC-3 155.52 MHz
and derivatives:
6.48 MHz
19.44 MHz
25.92 MHz
38.88 MHz
51.84 MHz
77.76 MHz
155.52 MHz
311.04 MHz
Inputs: 4 x TTL
Programmable;
2 kHz
4 kHz
N x 8 kHz
1.544/2.048 MHz
6.48 MHz
19.44 MHz
25.92 MHz
38.88 MHz
51.84 MHz
77.76 MHz
8 kHz
(FrSync)
2 kHz
(MFrSync)
Output
Ports
Priority
Table
Register Set
Serial
Port
OCXO or
TCXO
T4 DPLL/Freq. Synthesis
T0 DPLL/Freq. Synthesis


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