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ACS8522 Datasheet(PDF) 46 Page - Semtech Corporation |
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ACS8522 Datasheet(HTML) 46 Page - Semtech Corporation |
46 / 118 page ADVANCED COMMUNICATIONS FINAL DATASHEET Revision 5/November 2006 © Semtech Corp. Page 46 www.semtech.com ACS8522 SETS LITE Address (hex): 03 Register Name test_register1 Description (R/W) Register containing various test controls (not normally used). Default Value 0001 0000 Bit 7Bit 6 Bit 5Bit 4 Bit 3 Bit 2Bit 1Bit 0 phase_alarm disable_180 resync_analog Set to zero 8k Edge Polarity Set to zero Set to zero Bit No. Description Bit Value Value Description 7 phase_alarm (phase alarm (R/O)) Instantaneous result from T0 DPLL 0 1 T0 DPLL reporting phase locked. T0 DPLL reporting phase lost. 6 disable_180 Normally the DPLL will try to lock to the nearest edge (±180 °) for the first 2 seconds when locking to a new reference. If the DPLL does not determine that it is phase locked after this time, then the capture range reverts to ±360 °, which corresponds to frequency and phase locking. Forcing the DPLL into frequency locking mode may reduce the time to frequency lock to a new reference by up to 2 seconds. However, this may cause an unnecessary phase shift of up to 360 ° when the new and old references are very close in frequency and phase. 0 1 T0 DPLL automatically determines frequency lock enable. T0 DPLL forced to always frequency and phase lock. 5Not used. - - 4 resync_analog (analog dividers re-synchronization) The analog output dividers include a synchronization mechanism to ensure phase lock at low frequencies between the input and the output. 0 1 Analog divider only synchronized during first 2 seconds after power-up. Analog dividers always synchronized.This keeps the clocks divided down from the APLL output, in sync with equivalent frequency digital clocks in the DPLL. Hence ensuring that 6.48 MHz output clocks, and above, are in sync with the DPLL even though only a 77.76 MHz clock drives the APLL. 3Test Control Leave unchanged or set to 0 0- 2 8k Edge Polarity When lock 8k mode is selected for the current input reference source, this bit allows the system to lock on either the rising or the falling edge of the input clock. 0 1 Lock to falling clock edge. Lock to rising clock edge. 1Test Control Leave unchanged or set to zero 0- 0Test Control Leave unchanged or set to zero 0- |
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