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ACS8510 Rev2.1 SETS

ADVANCED COMMUNICATIONS

FINAL

Revision 2.00/September 2003

Semtech Corp.

List of T

List of T

List of T

List of T

List of Tables

ables

ables

ables

ables

Table 1. Power Pins .................................................................................................................................................................................... 6

Table 2. No Connections ............................................................................................................................................................................ 6

Table 3. Other Pins ..................................................................................................................................................................................... 7

Table 4. Input Reference Source Selection and Priority Table .......................................................................................................... 12

Table 5. Input ReferenceSource Jitter Tolerance ................................................................................................................................. 14

Table 6. Amplitude and Frequency Values for Jitter Tolerance ............................................................................................................ 15

Table 7. Amplitude and Frequency Values for Jitter Tolerance ............................................................................................................ 16

Table 8. Output Reference Source Selection Table ............................................................................................................................. 17

Table 9. Multiple E1/DS1 Output in Relation to Normal Outputs ..................................................................................................... 17

Table 10. Microprocessor Interface Mode Selection ......................................................................................................................... 21

Table 11. Register Map .......................................................................................................................................................................... 23

Table 12. Register Map Description ..................................................................................................................................................... 27

Table 13. Master-Slave Relationship .................................................................................................................................................... 46

Table 14. Absolute Maximum Ratings .................................................................................................................................................. 48

Table 15. Operating Conditions ............................................................................................................................................................. 48

Table 16. DC Characteristics: TTL Input Port ....................................................................................................................................... 48

Table 17. DC Characteristics: TTL Input Port with Internal Pull-up .................................................................................................... 49

Table 18. DC Characteristics: TTL Input Port with Internal Pull-down ............................................................................................... 49

Table 18. DC Characteristics: TTL Output Port .................................................................................................................................... 49

Table 20. DC Characteristics: PECL Input/Output Port ...................................................................................................................... 50

Table 21. DC Characteristics: LVDS Input/Output Port ...................................................................................................................... 52

Table 22. DC Characteristics: AMI Input/Output Port ........................................................................................................................ 54

Table 23. DC Characteristics: Ouput Jitter Generation (Test Definition G.813) ............................................................................. 57

Table 24. DC Characteristics: Ouput Jitter Generation (Test Definition G.812) ............................................................................. 57

Table 25. DC Characteristics: Ouput Jitter Generation (Test Definition ETS-300-462-3) .............................................................. 58

Table 26. DC Characteristics: Ouput Jitter Generation (Test Definition GR-253-CORE) ............................................................... 58

Table 27. DC Characteristics: Ouput Jitter Generation (Test Definition AT&T 62411) ................................................................... 59

Table 28. DC Characteristics: Ouput Jitter Generation (Test Definition G.742) .............................................................................. 59

Table 29. DC Characteristics: Ouput Jitter Generation (Test Definition TR-NWT-000499) ........................................................... 59

Table 30. DC Characteristics: Ouput Jitter Generation (Test Definition GR-1244-CORE) ............................................................. 60

Table 31. JTAG Timing (for use with Figure 17) ................................................................................................................................... 61

Table 32. Read Access Timing in MOTOROLA Mode (for use with Figure 19) ................................................................................. 63

Table 33. Write Access Timing in MOTOROLA Mode (for use with Figure 20) ................................................................................ 64

Table 34. Read Access Timing in INTEL Mode (for use with Figure 21) ............................................................................................ 65

Table 35. Write Access Timing in INTEL Mode (for use with Figure 22) ........................................................................................... 66

Table 36. Read Access Timing in MULTIPLEXED Mode (for use with Figure 23) ............................................................................. 67

Table 37. Write Access Timing in MULTIPLEXED Mode (for use with Figure 24) ............................................................................. 68

Table 38. Read Access Timing in SERIAL Mode (for use with Figure 25) ......................................................................................... 70

Table 39. Write Access Timing in SERIAL Mode (for use with Figure 26) ........................................................................................ 70

Table 40. Access Timing in EPROM Mode (for use with Figure 27) .................................................................................................. 71

Table 41. 100 Pin LQFP Package Dimension Data (for use with Figure 28) ................................................................................... 73