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ACS8509 Datasheet(PDF) 55 Page - Semtech Corporation |
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ACS8509 Datasheet(HTML) 55 Page - Semtech Corporation |
55 / 68 page ADVANCED COMMUNICATIONS FINAL DATASHEET Revision 2.00/January 2006 © Semtech Corp. Page 55 www.semtech.com ACS8509 SETS Intel Mode In Intel mode, the device is configured to interface with a microprocessor using a 80x86 type bus as parallel data + address. Figure 17 and Figure 18 show the timing diagrams of read and write accesses for this mode. Figure 17 Read Access Timing in INTEL Mode Note: (i) Timing with RDY. If RDY not used, tpw1 becomes 180 ns. Table 34 Read Access Timing in INTEL Mode (for use with Figure 17) Symbol Parameter MIN TYP MAX tsu1 Setup A valid to CSBfalling edge 0 ns - - tsu2 Setup CSBfalling edge to RDBfalling edge 0 ns - - td1 Delay RDBfalling edge to AD valid - - 177 ns td2 Delay CSBfalling edge to RDY active - - 13 ns td3 Delay RDBfalling edge to RDYfalling edge -- 14 ns td4 Delay RDBrising edge to AD high-Z - - 10 ns td5 Delay CSBrising edge to RDY high-Z - - 9 ns tpw1 RDB Low time 486 ns(i) -- tpw2 RDY Low time 310 ns - 472 ns th1 Hold A valid after RDBrising edge 0 ns - - th2 Hold CSB Low after RDBrising edge 0 ns - - th3 Hold RDB Low after RDYrising edge 0 ns - - tp Time between consecutive accesses (RDBrising edge to RDBfalling edge, or RDBrising edge to WRBfalling edge) 320 ns - - F8110D_009ReadAccIntel_01 CSB address Z Z data WRB RDB tpw1 th2 th1 tsu2 A tsu1 td3 tpw2 th3 AD td1 td4 RDY td2 td5 |
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