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EP1AGX50CF484C6N Datasheet(PDF) 22 Page - Altera Corporation |
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EP1AGX50CF484C6N Datasheet(HTML) 22 Page - Altera Corporation |
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22 / 296 page  2–14 Altera Corporation Arria GX Device Handbook, Volume 1 May 2008 Transceivers If a design uses external termination, the receiver must be externally terminated and biased to 0.85 V or 1.2 V. Figure 2–12 shows an example of an external termination and biasing circuit. Figure 2–12. External Termination and Biasing Circuit Programmable Equalizer The Arria GX receivers provide a programmable receiver equalization feature to compensate for the effects of channel attenuation for high- speed signaling. PCB traces carrying these high-speed signals have low- pass filter characteristics. Impedance mismatch boundaries can also cause signal degradation. Equalization in the receiver diminishes the lossy attenuation effects of the PCB at high frequencies. The receiver equalization circuit is comprised of a programmable amplifier. Each stage is a peaking equalizer with a different center frequency and programmable gain. This allows varying amounts of gain to be applied, depending on the overall frequency response of the channel loss. Channel loss is defined as the summation of all losses through the PCB traces, vias, connectors, and cables present in the physical link. The Quartus II software allows five equalization settings for Arria GX devices. Receiver PLL and Clock Recovery Unit (CRU) Each transceiver block has four receiver PLLs and CRU units, each of which is dedicated to a receiver channel. The receiver PLL is fed by an input reference clock. The receiver PLL, in conjunction with the CRU, Transmission Line C1 R1/R2 = 1K VDD × {R2/(R1 + R 2)} = 0.85/1.2 V 50- Ω Termination Resistance R1 R2 VDD Receiver External Termination and Biasing Arria GX Device Receiver External Termination and Biasing RXIP RXIN Receiver |
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