9

FN6829.3

July 9, 2009

Block Diagram

Theory of Operation

The ISL9104, ISL9104A is a step-down switching regulator

optimized for battery-powered handheld applications. The

regulator operates at typical 4.3MHz fixed switching

frequency under heavy load condition to allow small external

inductor and capacitors to be used for minimal printed-circuit

board (PCB) area. At light load, the regulator can

automatically enter the skip mode (PFM mode) to reduce the

switching frequency to minimize the switching loss and to

maximize the battery life. The quiescent current under skip

mode under no load and no switch condition is typically only

20µA. The supply current is typically only 0.05µA when the

regulator is disabled.

PWM Control Scheme

The ISL9104, ISL9104A uses the peak-current-mode

pulse-width modulation (PWM) control scheme for fast

transient response and pulse-by-pulse current limiting.

Figure 22 shows the circuit functional block diagram. The

current loop consists of the oscillator, the PWM comparator

COMP, current sensing circuit, and the slope compensation

for the current loop stability. The current sensing circuit

consists of the resistance of the P-Channel MOSFET when it

is turned on and the Current Sense Amplifier (CSA). The

control reference for the current loops comes from the Error

Amplifier (EAMP) of the voltage loop.

SW

+

CSA

+

+

OCP

VREF1

SKIP

+

X

SLOPE

COMP

SOF

T

STAR

T

SOFT-

START

VREF

EAMP

COMP

PWM/PFM

LOGIC

CONTROLLER

PROTECTION

DRIVER

FB

SHUTDOWN

VIN

GND

OSCILLATOR

ZERO-CROSS

SENSING

BLEEDING

FET

*NOTE

BANDGAP

SCP

+

EN

SHUTDOWN

100

Ω

VREF2

VREF3

*NOTE: FOR FIXED OUTPUT OPTIONS ONLY

FIGURE 22. FUNCTIONAL BLOCK DIAGRAM

NOTE: For Adjustable output version, the internal feedback resistor divider is disabled and the FB pin is directly connected

to the error amplifier.

ISL9104, ISL9104A