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MG2RTP Datasheet(PDF) 2 Page - ATMEL Corporation |
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MG2RTP Datasheet(HTML) 2 Page - ATMEL Corporation |
2 / 14 page 2 4116M–AERO–06/06 MG2RTP The MG2RTP Library allows straight forward migration from the MG1, MG1RT, MG2 and MG2RT Sea of Gates. A netlist based on this library can be simulated as either MG2RTP or MG2RT. It can also be sim- ulated as MG2, provided there are no SEU Free cells. Table 1. List of Available MG2RTP Matrices Note: 1. Not available for new designs. Libraries The MG2RTP cell library has been designed to take full advantage of the features offered by both logic and test synthesis tools. Design testability is assured by the full support of SCAN, JTAG (IEEE 1149) and BIST methodologies. More complex macro functions are available in VHDL, such as Two-Wire Interface (TWI), UART, Timer. Block Generators Block generators are used to create a customer specific simulation model and metallisation pat- tern for regular functions like RAM and DPRAM. The basic cell architecture allows one bit per cell for RAM and DPRAM. The main characteristics of these generators are summarized below. Type Total Gates Typical Usable Gates Maximum Programmable I/Os Total Pads MG2044P 44616 31200 146 165 MG2142P 142128 99500 262 281 MG2270P(1) 270015 189000 360 377 Function Maximum Size (bits) Bits/Word Typical Characteristics (16K bits) at5V Access Time (ns) Used cells RAM 32K 1-36 12 20K DPRAM 32K 1-36 14 23K |
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