Features

– 420 ps Max NAND2 Propagation Delay at 4.5V, 670 ps at 2.7 and FO = 5

– Min 650 MHz Toggle Frequency at 4.5V and 340 MHz at 2.7V

– 1.96 µW/Gate/MHz at 5V

– 0.6 µW/Gate/MHz at 3V

– I/O with Slew Rate Control

– Internal Decoupling

– Signal Filtering between Periphery and Core

– Application Dependent Supply Routing and Several Independent Supply Sources

Power Management

see MG2RT and MG2RTP Specifications)

Description

The MG2 series is a 0.5 micron, array based, CMOS product family. Several arrays up

to 480K gates cover most system integration needs. The MG2 is manufactured using

a 0.5 micron drawn, 3 metal layers CMOS process, called SCMOS 3/2.

The base cell architecture of the MG2 series provides high routability of logic with

extremely dense compiled memories: RAM and DPRAM. ROM can be generated

using synthesis tools.

Accurate control of clock distribution can be achieved by PLL hardware and CTS

(Clock Tree Synthesis) software. New noise prevention techniques are applied in the

array and in the periphery: three or more independent supplies, internal decoupling,

customization dependent supply routing, noise filtering, skew controlled I/Os, low

swing differential I/Os, all contribute to improve the noise immunity and reduce the

emission level.

The MG2 is supported by an advanced software environment based on industry stan-

dards linking proprietary and commercial tools. Verilog, Modelsim, Design Compiler

are the reference front-end tools. Floor planning associated with timing driven layout

provides a short back-end cycle.

The MG2 library allows straight forward migration from MG1 Sea of Gates. A netlist

based on this library can be simulated as either MG2, or MG2RT or MG2RTP.

4137O–AERO–06/05

350K Used Gates

0.5 µm CMOS

Sea of Gates

MG2