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T89C51AC2-SLSIM Datasheet(PDF) 7 Page - ATMEL Corporation |
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T89C51AC2-SLSIM Datasheet(HTML) 7 Page - ATMEL Corporation |
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7 / 121 page  7 A/T89C51AC2 4127H–8051–02/08 Figure 2. Port 0 Structure Notes: 1. Port 0 is precluded from use as general-purpose I/O Ports when used as address/data bus drivers. 2. Port 0 internal strong pull-ups assist the logic-one output for memory bus cycles only. Except for these bus cycles, the pull-up FET is off, Port 0 outputs are open-drain. Figure 3. Port 2 Structure Notes: 1. Port 2 is precluded from use as general-purpose I/O Ports when as address/data bus drivers. 2. Port 2 internal strong pull-ups FET (P1 in FiGURE) assist the logic-one output for memory bus cycle. When Port 0 and Port 2 are used for an external memory cycle, an internal control signal switches the output-driver input from the latch output to the internal address/data line. Read-Modify-Write Instructions Some instructions read the latch data rather than the pin data. The latch based instruc- tions read the data, modify the data and then rewrite the latch. These are called "Read- Modify-Write" instructions. Below is a complete list of these special instructions (see Table ). When the destination operand is a Port or a Port bit, these instructions read the latch rather than the pin: D Q P0.X LATCH INTERNAL WRITE TO LATCH READ PIN READ LATCH 0 1 P0.x (1) ADDRESS LOW/ DATA CONTROL VDD BUS (2) D Q P2.X LATCH INTERNAL WRITE TO LATCH READ PIN READ LATCH 0 1 P2.x (1) ADDRESS HIGH/ CONTROL BUS VDD INTERNAL PULL-UP (2) |
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