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AT45DB011D-SH-T Datasheet(PDF) 37 Page - ATMEL Corporation |
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AT45DB011D-SH-T Datasheet(HTML) 37 Page - ATMEL Corporation |
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37 / 52 page  37 3639E–DFLASH–5/08 AT45DB011D 21.5 Utilizing the RapidS Function To take advantage of the RapidS function's ability to operate at higher clock frequencies, a full clock cycle must be used to transmit data back and forth across the serial bus. The DataFlash is designed to always clock its data out on the falling edge of the SCK signal and clock data in on the rising edge of SCK. For full clock cycle operation to be achieved, when the DataFlash is clocking data out on the falling edge of SCK, the host controller should wait until the next falling edge of SCK to latch the data in. Similarly, the host controller should clock its data out on the rising edge of SCK in order to give the DataFlash a full clock cycle to latch the incoming data in on the next rising edge of SCK. Figure 21-1. RapidS Mode SCK MOSI MISO 1 234567 81 234567 8 MOSI = Master Out, Slave In MISO = Master In, Slave Out The Master is the host controller and the Slave is the DataFlash The Master always clocks data out on the rising edge of SCK and always clocks data in on the falling edge of SCK. The Slave always clocks data out on the falling edge of SCK and always clocks data in on the rising edge of SCK. A. Master clocks out first bit of BYTE-MOSI on the rising edge of SCK. B. Slave clocks in first bit of BYTE-MOSI on the next rising edge of SCK. C. Master clocks out second bit of BYTE-MOSI on the same rising edge of SCK. D. Last bit of BYTE-MOSI is clocked out from the Master. E. Last bit of BYTE-MOSI is clocked into the slave. F. Slave clocks out first bit of BYTE-SO. G. Master clocks in first bit of BYTE-SO. H. Slave clocks out second bit of BYTE-SO. I. Master clocks in last bit of BYTE-SO. A B CD E F G 1 H BYTE-MOSI MSB LSB BYTE-SO MSB LSB Slave CS I |
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