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VIPER20B Datasheet(PDF) 12 Page - STMicroelectronics |
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VIPER20B Datasheet(HTML) 12 Page - STMicroelectronics |
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12 / 17 page 
consumption and also provided to the external capacitor connected to the VDD pin. As soon as the voltage on this pin reaches the high voltage threshold VDDon of the UVLO logic, the device turns into active mode and starts switching. The start up current generator is switched off, and the converter should normally provide the needed current on the VDD pin through the auxiliary winding of the transformer, as shown on figure 12. In case of abnormal condition where the auxiliary winding is unable to provide the low voltage supply current to the VDD pin (i.e. short circuit on the output of the converter), the external capacitor discharges itself down to the low threshold voltage VDDoff of the UVLO logic, and the device get back to the inactive state where the internal circuits are in standby mode and the start up current source is activated. The converter enters a endless start up cycle, with a start-up duty cycle defined by the ratio of charging current towards discharging when the VIPer20B tries to start. This ratio is fixed by design to 2 to 14, which gives a 13% start up duty cycle while the power dissipation at start up is approximately 1W, for a 230 Vrms input voltage. This low value of start-up duty cycle prevents the stress of the output rectifiers and of the transformer when in short circuit. The external capacitor CVDD on the VDD pin must be sized according to the time needed by the converter to start up, when the device starts switching. This time tSS depends on many parameters, among which transformer design, output capacitors, soft start feature and compensation network implemented on the COMP pin. The following formula can be used for defining the minimum capacitor needed: CVDD > IDD tSS VDDhyst where: IDD is the consumption current on the VDD pin when switching. Refer to specified IDD1 and IDD2 values. tSS is the start up time of the converter when the device begins to switch. Worst case is generally at full load. VDDhyst is the voltage hysteresis of the UVLO logic. Refer to the minimum specified value. Soft start feature can be implemented on the COMP pin through a simple capacitor which will be also used as the compensation network. In this case, the regulation loop bandwidth is rather low, because of the large value of this capacitor. In case a large regulation loop bandwidth is mandatory, the schematics of figure 13 can be used. It mixes a high performance compensation Figure 12: Behaviour of the high voltage current source at start-up FC004 22 Ref. UNDERVOLTAGE LOCK OUT LOGIC 15 mA 1mA 3mA 2mA 15 mA VDD DRAIN SOUR CE VIPer Auxilia ry prima ry wind in g VDD t VDDoff VDDo n Sta rt up dut y cycle ~ 10 % CVDD VIPer20B / VIPer20BSP 12/17 |
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