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ATMEGA32-16AU Datasheet(PDF) 77 Page - ATMEL Corporation |
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ATMEGA32-16AU Datasheet(HTML) 77 Page - ATMEL Corporation |
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77 / 346 page  77 2503N–AVR–06/08 ATmega32(L) between OCR0 and TCNT0 when the counter increments, and setting (or clearing) the OC0 Register at compare match between OCR0 and TCNT0 when the counter decrements. The PWM frequency for the output when using phase correct PWM can be calculated by the follow- ing equation: The N variable represents the prescale factor (1, 8, 64, 256, or 1024). The extreme values for the OCR0 Register represent special cases when generating a PWM waveform output in the phase correct PWM mode. If the OCR0 is set equal to BOTTOM, the out- put will be continuously low and if set equal to MAX the output will be continuously high for non- inverted PWM mode. For inverted PWM the output will have the opposite logic values. At the very start of period 2 in Figure 33 OCn has a transition from high to low even though there is no Compare Match. The point of this transition is to guarantee symmetry around BOTTOM. There are two cases that give a transition without Compare Match: • OCR0A changes its value from MAX, like in Figure 33. When the OCR0A value is MAX the OCn pin value is the same as the result of a down-counting Compare Match. To ensure symmetry around BOTTOM the OCn value at MAX must correspond to the result of an up- counting Compare Match. • The timer starts counting from a value higher than the one in OCR0A, and for that reason misses the Compare Match and hence the OCn change that would have happened on the way up. Timer/Counter Timing Diagrams The Timer/Counter is a synchronous design and the timer clock (clk T0) is therefore shown as a clock enable signal in the following figures. The figures include information on when Interrupt Flags are set. Figure 34 contains timing data for basic Timer/Counter operation. The figure shows the count sequence close to the MAX value in all modes other than phase correct PWM mode. Figure 34. Timer/Counter Timing Diagram, no Prescaling Figure 35 shows the same timing data, but with the prescaler enabled. f OCnPCPWM f clk_I/O N 510 ⋅ ------------------ = clk Tn (clk I/O/1) TOVn clk I/O TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 |
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