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AT32UC3B1128-AUT Datasheet(PDF) 5 Page - ATMEL Corporation |
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AT32UC3B1128-AUT Datasheet(HTML) 5 Page - ATMEL Corporation |
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5 / 65 page  5 32059GS–AVR32–04/08 AT32UC3B 3.1 Processor and architecture 3.1.1 AVR32UC CPU • 32-bit load/store AVR32A RISC architecture. – 15 general-purpose 32-bit registers. – 32-bit Stack Pointer, Program Counter and Link Register reside in register file. – Fully orthogonal instruction set. – Privileged and unprivileged modes enabling efficient and secure Operating Systems. – Innovative instruction set together with variable instruction length ensuring industry leading code density. – DSP extention with saturating arithmetic, and a wide variety of multiply instructions. • 3 stage pipeline allows one instruction per clock cycle for most instructions. – Byte, half-word, word and double word memory access. – Multiple interrupt priority levels. • MPU allows for operating systems with memory protection. 3.1.2 Debug and Test system • IEEE1149.1 compliant JTAG and boundary scan • Direct memory access and programming capabilities through JTAG interface • Extensive On-Chip Debug features in compliance with IEEE-ISTO 5001-2003 (Nexus 2.0) Class 2+ – Low-cost NanoTrace supported. • Auxiliary port for high-speed trace information • Hardware support for 6 Program and 2 data breakpoints • Unlimited number of software breakpoints supported • Advanced Program, Data, Ownership, and Watchpoint trace supported 3.1.3 Peripheral DMA Controller (PDCA) • Transfers from/to peripheral to/from any memory space without intervention of the processor. • Next Pointer Support, forbids strong real-time constraints on buffer management. • 7 channels that can be dynamically attributed to – all USARTs – the Serial Synchronous Controller – the Serial Peripheral Interface –the ADC – the TWI Interface 3.1.4 Bus system • High Speed Bus (HSB) matrixs – Handles Requests from Masters: the CPU (instruction and Data Fetch), PDCA, USBB, CPU SAB, Slaves: the internal Flash, internal SRAM, Peripheral Bus A, Peripheral Bus B, USBB. – Round-Robin Arbitration (three modes supported: no default master, last accessed default master, fixed default master) – Burst Breaking with Slot Cycle Limit – One Address Decoder Provided per Master – Peripheral Bus A able to run on at divided bus speeds compared to the High Speed Bus – All modules connected to the same bus use the same clock, but the clock to each module can be individually shut off by the Power Manager. |
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